公开(公告)号：US20220181459A1

公开(公告)日：2022-06-09

申请号：US17383022

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Dae Cho ,  Ki Hwan Kim ,  Sung Uk Jang ,  Su Jin Jung

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: An integrated circuit device includes a substrate having source and drain recesses therein that are lined with respective silicon-germanium liners and filled with doped semiconductor source and drain regions. A stacked plurality of semiconductor channel layers are provided, which are separated vertically from each other within the substrate by corresponding buried insulated gate electrode regions that extend laterally between the silicon-germanium liners. An insulated gate electrode is provided on an uppermost one of the plurality of semiconductor channel layers. The silicon-germanium liners may be doped with carbon.

公开(公告)号：US11257905B2

公开(公告)日：2022-02-22

申请号：US16386459

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Seung Hun Lee ,  Su Jin Jung ,  Young Dae Cho

IPC: H01L29/08 ,  H01L29/786 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/82 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.