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公开(公告)号:US20230116342A1
公开(公告)日:2023-04-13
申请号:US17829781
申请日:2022-06-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Won Hee Choi , Sung Uk Jang , Dong Suk Shin , Bong Jin Kuh , Kong Soo Lee
IPC: H01L29/78 , H01L29/06 , H01L29/786 , H01L29/423 , H01L27/108
Abstract: A semiconductor device is provided. A semiconductor device includes: a first active pattern spaced apart from a substrate and extending in a first direction; a second active pattern spaced apart further from the substrate than the first active pattern and extending in the first direction; a gate structure on the substrate, the gate structure extending in a second direction crossing the first direction and penetrating the first active pattern and the second active pattern; a first source/drain region on at least one side surface of the gate structure and connected to the first active pattern; a second source/drain region on at least one side surface of the gate structure and connected to the second active pattern; and a buffer layer between the substrate and the first active pattern, the buffer layer containing germanium.
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公开(公告)号:US11031502B2
公开(公告)日:2021-06-08
申请号:US16708717
申请日:2019-12-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Uk Jang , Young Dae Cho , Ki Hwan Kim , Su Jin Jung
IPC: H01L29/78 , H01L29/08 , H01L29/786 , H01L29/423
Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.
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公开(公告)号:US11728434B2
公开(公告)日:2023-08-15
申请号:US17011221
申请日:2020-09-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seok Hoon Kim , Dong Myoung Kim , Dong Suk Shin , Seung Hun Lee , Cho Eun Lee , Hyun Jung Lee , Sung Uk Jang , Edward Nam Kyu Cho , Min-Hee Choi
IPC: H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/768 , H01L21/02 , H01L29/423 , H01L29/165 , H01L27/088 , H01L29/08 , H01L29/49 , H01L27/12
CPC classification number: H01L29/7855 , H01L21/02532 , H01L21/76871 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/165 , H01L29/4232 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L21/02645 , H01L27/1211 , H01L29/4966 , H01L29/66545
Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
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公开(公告)号:US11670716B2
公开(公告)日:2023-06-06
申请号:US17337759
申请日:2021-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Uk Jang , Young Dae Cho , Ki Hwan Kim , Su Jin Jung
IPC: H01L29/78 , H01L29/08 , H01L29/786 , H01L29/423
CPC classification number: H01L29/7851 , H01L29/0847 , H01L29/42392 , H01L29/78696
Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.
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公开(公告)号:US12132113B2
公开(公告)日:2024-10-29
申请号:US18204469
申请日:2023-06-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Uk Jang , Young Dae Cho , Ki Hwan Kim , Su Jin Jung
IPC: H01L29/78 , H01L29/08 , H01L29/423 , H01L29/786
CPC classification number: H01L29/7851 , H01L29/0847 , H01L29/42392 , H01L29/78696
Abstract: A semiconductor device and a method for making a semiconductor device. The semiconductor device includes an active region on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers and including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically.
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公开(公告)号:US11239363B2
公开(公告)日:2022-02-01
申请号:US16598012
申请日:2019-10-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Uk Jang , Ki Hwan Kim , Su Jin Jung , Bong Soo Kim , Young Dae Cho
IPC: H01L29/78 , H01L29/66 , H01L29/08 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/24
Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.
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公开(公告)号:US10784379B2
公开(公告)日:2020-09-22
申请号:US15995414
申请日:2018-06-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seok Hoon Kim , Dong Myoung Kim , Dong Suk Shin , Seung Hun Lee , Cho Eun Lee , Hyun Jung Lee , Sung Uk Jang , Edward Nam Kyu Cho , Min-Hee Choi
IPC: H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/768 , H01L21/02 , H01L29/423 , H01L29/165 , H01L27/088 , H01L29/08 , H01L29/49 , H01L27/12
Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
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公开(公告)号:US11843053B2
公开(公告)日:2023-12-12
申请号:US17398550
申请日:2021-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Su Jin Jung , Ki Hwan Kim , Sung Uk Jang , Young Dae Cho
IPC: H01L29/06 , H01L29/786 , H01L29/423 , H01L29/66 , H01L21/02
CPC classification number: H01L29/78618 , H01L21/0259 , H01L29/0665 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/78696
Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.
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公开(公告)号:US20220181499A1
公开(公告)日:2022-06-09
申请号:US17398550
申请日:2021-08-10
Applicant: SAMSUNG ELECTRONICS co., LTD.
Inventor: Su Jin Jung , Ki Hwan Kim , Sung Uk Jang , Young Dae Cho
IPC: H01L29/786 , H01L29/06 , H01L29/423 , H01L21/02 , H01L29/66
Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.
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公开(公告)号:US20220181459A1
公开(公告)日:2022-06-09
申请号:US17383022
申请日:2021-07-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young Dae Cho , Ki Hwan Kim , Sung Uk Jang , Su Jin Jung
IPC: H01L29/423 , H01L29/786 , H01L29/06 , H01L29/08
Abstract: An integrated circuit device includes a substrate having source and drain recesses therein that are lined with respective silicon-germanium liners and filled with doped semiconductor source and drain regions. A stacked plurality of semiconductor channel layers are provided, which are separated vertically from each other within the substrate by corresponding buried insulated gate electrode regions that extend laterally between the silicon-germanium liners. An insulated gate electrode is provided on an uppermost one of the plurality of semiconductor channel layers. The silicon-germanium liners may be doped with carbon.
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