公开(公告)号：US11843053B2

公开(公告)日：2023-12-12

申请号：US17398550

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Jin Jung ,  Ki Hwan Kim ,  Sung Uk Jang ,  Young Dae Cho

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.

公开(公告)号：US20220181499A1

公开(公告)日：2022-06-09

申请号：US17398550

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS co., LTD.

Inventor： Su Jin Jung ,  Ki Hwan Kim ,  Sung Uk Jang ,  Young Dae Cho

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.

公开(公告)号：US20220181459A1

公开(公告)日：2022-06-09

申请号：US17383022

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Dae Cho ,  Ki Hwan Kim ,  Sung Uk Jang ,  Su Jin Jung

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08

Abstract: An integrated circuit device includes a substrate having source and drain recesses therein that are lined with respective silicon-germanium liners and filled with doped semiconductor source and drain regions. A stacked plurality of semiconductor channel layers are provided, which are separated vertically from each other within the substrate by corresponding buried insulated gate electrode regions that extend laterally between the silicon-germanium liners. An insulated gate electrode is provided on an uppermost one of the plurality of semiconductor channel layers. The silicon-germanium liners may be doped with carbon.

公开(公告)号：US11670716B2

公开(公告)日：2023-06-06

申请号：US17337759

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Young Dae Cho ,  Ki Hwan Kim ,  Su Jin Jung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.

公开(公告)号：US09679978B2

公开(公告)日：2017-06-13

申请号：US15272456

申请日：2016-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Jung Gun You ,  Gi Gwan Park ,  Dong Suk Shin ,  Jin Wook Kim

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having first and second regions, a first fin-type pattern and a second fin-type pattern formed in the first region and extending in a first direction, and a third fin-type pattern and a fourth fin-type pattern formed in the second region and extending in a third direction. A first source/drain is formed on the first fin-type pattern and a second source/drain region is formed on the second fin-type pattern. Each of first and second source/drains have a cross section defining a same convex polygonal shape. A third source/drain is formed on the third fin-type pattern and a fourth source/drain region is formed on the fourth fin-type pattern. Cross-sections of the third and fourth source/drains define different convex polygonal shapes from one another.

公开(公告)号：US12245440B2

公开(公告)日：2025-03-04

申请号：US17692369

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Hwan Kim ,  Jeong Ho Yoo ,  Cho Eun Lee ,  Yong Uk Jeon ,  Young Dae Cho

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66 ,  H10D30/67 ,  H10D64/01

Abstract: A semiconductor includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern, the source/drain pattern being in contact with the sheet patterns, and gate structures on opposite sides of the source/drain pattern, the gate structures being spaced apart from each other along a second direction and including gate electrodes that surround the sheet patterns, wherein the source/drain pattern includes a first epitaxial region having at least one of antimony and bismuth, the first epitaxial region having a bottom part in contact with the lower pattern, but not with the sheet patterns, and a thickness of the bottom part increasing and decreasing away from the gate structures in the second direction, and a second epitaxial region on the first epitaxial region, the second epitaxial region including phosphorus.

公开(公告)号：USRE49963E1

公开(公告)日：2024-05-07

申请号：US17155615

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Gigwan Park ,  Junggun You ,  DongSuk Shin ,  Jin-Wook Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H10B10/00 ,  H01L27/12 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66636 ,  H10B10/12 ,  H10B10/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

公开(公告)号：US20240063262A1

公开(公告)日：2024-02-22

申请号：US18127298

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Uk Jeon ,  Kyung Ho Kim ,  Ki Hwan Kim ,  Kang Hun Moon ,  Cho Eun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66553 ,  H01L27/092

Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern extending in on a substrate; nanosheets stacked on the active pattern; a gate electrode on the active pattern and surrounding the nanosheets; a source/drain trench on the active pattern adjacent the gate electrode; and a source/drain region in the source/drain trench, The source/drain region includes: a first layer provided along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein; a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein; and a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein.

公开(公告)号：US11031502B2

公开(公告)日：2021-06-08

申请号：US16708717

申请日：2019-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk Jang ,  Young Dae Cho ,  Ki Hwan Kim ,  Su Jin Jung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.

公开(公告)号：US10784376B2

公开(公告)日：2020-09-22

申请号：US16450193

申请日：2019-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Gigwan Park ,  Junggun You ,  DongSuk Shin ,  Jin-Wook Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.