公开(公告)号：US12205640B2

公开(公告)日：2025-01-21

申请号：US17375993

申请日：2021-07-14

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau ,  Christopher J. Petti

IPC: G11C13/00 ,  G06F11/10 ,  G11C11/16

Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.

公开(公告)号：US20210343338A1

公开(公告)日：2021-11-04

申请号：US17375993

申请日：2021-07-14

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau ,  Christopher J. Petti

IPC: G11C13/00 ,  G06F11/10 ,  G11C11/16

Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.

公开(公告)号：US20210249073A1

公开(公告)日：2021-08-12

申请号：US17245651

申请日：2021-04-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C13/00 ,  G11C11/16 ,  H01L27/22 ,  H01L27/24

Abstract: An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.