公开(公告)号：US11004508B2

公开(公告)日：2021-05-11

申请号：US16556376

申请日：2019-08-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02

Abstract: A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.

公开(公告)号：US11972787B2

公开(公告)日：2024-04-30

申请号：US17824806

申请日：2022-05-25

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Michael K. Grobis ,  Ward Parkinson ,  Nathan Franklin

IPC: G06F11/10 ,  G11C11/16

CPC classification number: G11C11/1659 ,  G06F11/1044 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

公开(公告)号：US11355188B2

公开(公告)日：2022-06-07

申请号：US17245651

申请日：2021-04-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C11/16 ,  G11C13/00 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02

Abstract: An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.

公开(公告)号：US11081174B2

公开(公告)日：2021-08-03

申请号：US16912719

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhaoqiang Bai ,  Mac D. Apodaca ,  Michael K. Grobis ,  Michael Nicolas Albert Tran ,  Neil Leslie Robertson ,  Gerardo A. Bertero

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

公开(公告)号：US20210065791A1

公开(公告)日：2021-03-04

申请号：US16556376

申请日：2019-08-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C13/00 ,  G11C11/16 ,  H01L27/22 ,  H01L27/24

Abstract: A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.

公开(公告)号：US20230386543A1

公开(公告)日：2023-11-30

申请号：US17824806

申请日：2022-05-25

Applicant: SanDisk Technologies LLC

Inventor： Michael Nicolas Albert Tran ,  Michael K. Grobis ,  Ward Parkinson ,  Nathan Franklin

IPC: G11C11/16 ,  G06F11/10

CPC classification number: G11C11/1659 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G06F11/1044

Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

公开(公告)号：US20200006432A1

公开(公告)日：2020-01-02

申请号：US16021804

申请日：2018-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michael K. Grobis ,  Derek Stewart ,  Bruce D. Terris

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C13/00 ,  G11C11/16

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current.

公开(公告)号：US12205640B2

公开(公告)日：2025-01-21

申请号：US17375993

申请日：2021-07-14

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau ,  Christopher J. Petti

IPC: G11C13/00 ,  G06F11/10 ,  G11C11/16

Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.

公开(公告)号：US20210343338A1

公开(公告)日：2021-11-04

申请号：US17375993

申请日：2021-07-14

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau ,  Christopher J. Petti

IPC: G11C13/00 ,  G06F11/10 ,  G11C11/16

Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.

公开(公告)号：US20210249073A1

公开(公告)日：2021-08-12

申请号：US17245651

申请日：2021-04-30

Applicant: SanDisk Technologies LLC

Inventor： Michael K. Grobis ,  Daniel Bedau

IPC: G11C13/00 ,  G11C11/16 ,  H01L27/22 ,  H01L27/24

Abstract: An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.