公开(公告)号：US11600343B2

公开(公告)日：2023-03-07

申请号：US17329390

申请日：2021-05-25

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Tomer Eliash ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11565 ,  G11C11/56 ,  H01L25/065

Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

公开(公告)号：US11475958B2

公开(公告)日：2022-10-18

申请号：US17192598

申请日：2021-03-04

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-yuan Tseng ,  Swaroop Kaza ,  Tomer Eliash

IPC: G11C11/00 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24 ,  G11C16/26

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

公开(公告)号：US11386968B1

公开(公告)日：2022-07-12

申请号：US17149136

申请日：2021-01-14

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-yuan Tseng ,  Tomer Eliash

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/12 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/24

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in a plurality of planes. The apparatus also includes a control circuit coupled to the word lines and the bit lines and configured to determine whether a program operation of the memory cells involves all of the plurality of planes. In response to the program operation of the memory cells not involving all of the plurality of planes, the control circuit adjusts at least one of a bit line ramp rate of a bit line voltage applied to the bit lines and a word line ramp rate of at least one word line voltage applied to the word lines during the program operation based on a quantity of the plurality of planes associated with the memory cells being program-verified in the program operation.