公开(公告)号：US20220284965A1

公开(公告)日：2022-09-08

申请号：US17192598

申请日：2021-03-04

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-yuan Tseng ,  Swaroop Kaza ,  Tomer Eliash

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/30

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

公开(公告)号：US11972813B2

公开(公告)日：2024-04-30

申请号：US17556477

申请日：2021-12-20

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Swaroop Kaza ,  Laidong Wang

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3409

Abstract: A memory device with adaptive sense time tables is disclosed. In order to maintain a desired (initial or preset) threshold voltage distribution, the sense time is adjusted as the program-erase cycle count increases. The program-erase cycle process tends to wear down memory cells, causing the QPW window to expand and the threshold voltage to widen. However, by adjusting (i.e., reducing) the sense time for increased program-erase cycles, the QPW window and the threshold voltage can be at least substantially maintained. Additionally, systems and methods for adjusting sense time based on die-to-die variations are also disclosed.

公开(公告)号：US20230260584A1

公开(公告)日：2023-08-17

申请号：US17671015

申请日：2022-02-14

Applicant: SanDisk Technologies LLC

Inventor： JIACEN GUO ,  Swaroop Kaza

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3422 ,  G11C16/08 ,  H01L27/11582

Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.

公开(公告)号：US11862260B2

公开(公告)日：2024-01-02

申请号：US17671015

申请日：2022-02-14

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Swaroop Kaza

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  H10B43/27

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3422 ,  H10B43/27

Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.

公开(公告)号：US11923019B2

公开(公告)日：2024-03-05

申请号：US17670821

申请日：2022-02-14

Applicant: SanDisk Technologies LLC

Inventor： Xiaojia Jia ,  Swaroop Kaza ,  Laidong Wang ,  Jiacen Guo

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.

公开(公告)号：US11475958B2

公开(公告)日：2022-10-18

申请号：US17192598

申请日：2021-03-04

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Huai-yuan Tseng ,  Swaroop Kaza ,  Tomer Eliash

IPC: G11C11/00 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24 ,  G11C16/26

Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.

公开(公告)号：US10235294B1

公开(公告)日：2019-03-19

申请号：US15959445

申请日：2018-04-23

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Swaroop Kaza ,  Piyush Sagdeo

IPC: G11C11/34 ,  G06F12/0866 ,  G11C16/34 ,  G06F12/02

Abstract: Apparatuses and techniques are described for performing a pre-read operation in preparation for a read operation in a memory device. The pre-read operation transitions the memory cells from a first read condition to a second read condition so that their threshold voltages will be in a desired, predictable range when the read occurs. The pre-read operation can involve maintaining voltages on a selected word line and unselected word lines at specified levels and for a specified duration which is relatively long compared to a duration of the read operation. The word line voltages, in combination with bit line and source line voltages, provide the channels of a NAND string in a conductive state and gradually transitions the memory cells to the second read condition.