公开(公告)号：US12015025B2

公开(公告)日：2024-06-18

申请号：US17265549

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/866

CPC classification number: H01L27/0255 ,  H01L29/0692 ,  H01L29/66106 ,  H01L29/866

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

公开(公告)号：US20210358903A1

公开(公告)日：2021-11-18

申请号：US17266134

申请日：2019-11-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/866 ,  H01L29/74 ,  H01L21/266

Abstract: A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).

公开(公告)号：US11171223B2

公开(公告)日：2021-11-09

申请号：US16957600

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

公开(公告)号：US20210313312A1

公开(公告)日：2021-10-07

申请号：US17265541

申请日：2019-09-04

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/866 ,  H01L29/66

Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

公开(公告)号：US20210167191A1

公开(公告)日：2021-06-03

申请号：US17265587

申请日：2019-10-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan Gu ,  Shikang Cheng ,  Sen Zhang

IPC: H01L29/66 ,  H01L29/78

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.