公开(公告)号：US10522593B2

公开(公告)日：2019-12-31

申请号：US16117947

申请日：2018-08-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Gourvest ,  Yannick Le Friec ,  Laurent Favennec

IPC: H01L27/24 ,  H01L45/00

Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.

公开(公告)号：US20180374898A1

公开(公告)日：2018-12-27

申请号：US16117947

申请日：2018-08-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Gourvest ,  Yannick Le Friec ,  Laurent Favennec

IPC: H01L27/24 ,  H01L45/00

Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.

公开(公告)号：US20130288450A1

公开(公告)日：2013-10-31

申请号：US13855139

申请日：2013-04-02

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Daniel Benoit ,  Laurent Favennec

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76283

Abstract: A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO2 layer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiO2 layer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiO2 layer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiO2 layer; depositing a second silicon nitride layer and filling the trench with SiO2; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed.

Abstract translation: 一种用于形成填充有与单晶硅层和第一SiO 2层交叉并穿透硅载体的绝缘体的沟槽的方法，该方法包括以下步骤：在硅层上形成第二SiO 2层和第一氮化硅层 形成沟槽，并进行第一氧化处理以形成第三SiO 2层; 进行第二氧化处理，以在所述第一氮化硅层的暴露的表面上形成第四SiO 2层; 沉积第二氮化硅层并用SiO 2填充沟槽; 并且去除结构的上部直到硅层的上表面露出。