公开(公告)号：US20180090542A1

公开(公告)日：2018-03-29

申请号：US15452940

申请日：2017-03-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Gourvest ,  Yannick Le Friec ,  Laurent Favennec

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.

公开(公告)号：US10892292B2

公开(公告)日：2021-01-12

申请号：US16386826

申请日：2019-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel Benoit ,  Olivier Hinsinger ,  Emmanuel Gourvest

IPC: H01L27/146

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

公开(公告)号：US20170040285A1

公开(公告)日：2017-02-09

申请号：US15225164

申请日：2016-08-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Francois Guyader ,  Emmanuel Gourvest ,  Patrick Gros D'aillon

IPC: H01L23/00 ,  H01L21/78 ,  H01L27/146

CPC classification number: H01L24/83 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L27/1462 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/27845 ,  H01L2224/29082 ,  H01L2224/83031 ,  H01L2224/83894

Abstract: A planar layer of a selected material is formed on a surface of a wafer exhibiting recesses. The formation process including the steps of: a) depositing a first layer of the selected material on the surface; b) performing a chemical mechanical polishing of the first layer; c) depositing a second layer of the selected material on the first layer; and d) performing a chemical mechanical polishing of the second layer.

Abstract translation: 在显示凹槽的晶片的表面上形成所选材料的平面层。 形成方法包括以下步骤：a）将所选材料的第一层沉积在表面上; b）对第一层进行化学机械抛光; c）在第一层上沉积所选材料的第二层; 和d）对所述第二层进行化学机械抛光。

公开(公告)号：US10304893B2

公开(公告)日：2019-05-28

申请号：US15592437

申请日：2017-05-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel Benoit ,  Olivier Hinsinger ,  Emmanuel Gourvest

IPC: H01L27/146

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

公开(公告)号：US20180102385A1

公开(公告)日：2018-04-12

申请号：US15592437

申请日：2017-05-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel Benoit ,  Olivier Hinsinger ,  Emmanuel Gourvest

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14609 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14698

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

公开(公告)号：US10522593B2

公开(公告)日：2019-12-31

申请号：US16117947

申请日：2018-08-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Gourvest ,  Yannick Le Friec ,  Laurent Favennec

IPC: H01L27/24 ,  H01L45/00

Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.

公开(公告)号：US20180374898A1

公开(公告)日：2018-12-27

申请号：US16117947

申请日：2018-08-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Gourvest ,  Yannick Le Friec ,  Laurent Favennec

IPC: H01L27/24 ,  H01L45/00

Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.