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公开(公告)号：US20180090542A1
公开(公告)日：2018-03-29
申请号：US15452940
申请日：2017-03-08
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Gourvest , Yannick Le Friec , Laurent Favennec
CPC classification number: H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.
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公开(公告)号：US10522593B2
公开(公告)日：2019-12-31
申请号：US16117947
申请日：2018-08-30
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Gourvest , Yannick Le Friec , Laurent Favennec
Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.
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公开(公告)号：US20180374898A1
公开(公告)日：2018-12-27
申请号：US16117947
申请日：2018-08-30
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Gourvest , Yannick Le Friec , Laurent Favennec
Abstract: Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.
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