公开(公告)号：US20200227382A1

公开(公告)日：2020-07-16

申请号：US16835793

申请日：2020-03-31

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/31

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20240038644A1

公开(公告)日：2024-02-01

申请号：US18377962

申请日：2023-10-09

Applicant: STMicroelectronics (Grenoble 2)SAS

Inventor： Romain COFFY ,  Fabien QUERCIA

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/22

CPC classification number: H01L23/49811 ,  H01L21/4817 ,  H01L21/4853 ,  H01L23/552 ,  H01L23/66 ,  H01L24/48 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/48227

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

公开(公告)号：US20230318165A1

公开(公告)日：2023-10-05

申请号：US18119026

申请日：2023-03-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Ouafa HAJJI ,  Asma HAJJI ,  Fabien QUERCIA

IPC: H01Q1/22 ,  H01L23/58 ,  H01L23/544 ,  H01L21/56 ,  H01Q1/48

CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/544 ,  H01L23/585 ,  H01Q1/48 ,  H01L24/16 ,  H01L2223/54426

Abstract: An electronic device includes an electronic integrated circuit chip assembled on a first region of a substrate. A radiation element of an antenna is mounted to the substrate in a manner where it is separated from the substrate by a second layer of a second dielectric material, and i\s further offset with respect to the first region of the substrate so that the radiation element does not cover the electronic integrated circuit chip. A first coating layer of a first coating material covers at least a surface of the electronic integrated circuit chip facing away from the substrate further covers a surface of the radiation element facing away from the substrate.

公开(公告)号：US20230081711A1

公开(公告)日：2023-03-16

申请号：US17943885

申请日：2022-09-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Didier CAMPOS ,  Fabien QUERCIA ,  Justin CATANIA

IPC: B23K20/00 ,  B23K20/10

Abstract: A wire bonding tool includes a tool body with a tubular cavity extending through the tool body and a distal end. The distal end includes a flared opening at an end of the tubular cavity. The tool body further includes at least one protrusion at a level of the distal end.

公开(公告)号：US20220157683A1

公开(公告)日：2022-05-19

申请号：US17523386

申请日：2021-11-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Younes BOUTALEB ,  Fabien QUERCIA ,  Asma HAJJI ,  Ouafa HAJJI

IPC: H01L23/31

Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.