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11.发明授权公开(公告)号：US10209961B2
公开(公告)日：2019-02-19
申请号：US15056586
申请日：2016-02-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
Abstract: A method of verifying the sensitivity of an electronic circuit executing a modular exponentiation calculation in a first register and a second register, successively including, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of that of the first and second registers which contains the multiplier of the operation of the first step is disturbed, for each bit of the exponent, during the execution of the first step.
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公开(公告)号：US20170124323A1
公开(公告)日：2017-05-04
申请号：US15405044
申请日：2017-01-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
CPC classification number: G06F21/55 , G06F7/58 , G06F21/556
Abstract: A method for detecting a fault injection in a circuit, wherein a bit pattern is mixed in a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mixing.
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13.发明申请VERIFICATION OF THE SENSITIVITY OF AN ELECTRONIC CIRCUIT EXECUTING A MODULAR EXPONENTIATION CALCULATION 审中-公开执行模块化指令计算的电子电路的灵敏度验证公开(公告)号：US20170060535A1
公开(公告)日：2017-03-02
申请号：US15056586
申请日：2016-02-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
CPC classification number: G06F7/723 , G06F2207/7219 , H04L9/004 , H04L9/06
Abstract: A method of verifying the sensitivity of an electronic circuit executing a modular exponentiation calculation in a first register and a second register, successively including, for each bit of the exponent: a first step of multiplying the content of one of the registers, selected from among the first register and the second register according to the state of the bit of the exponent, by the content of the other one of the first and second registers, placing the result in said one of the registers; a second step of squaring the content of said other one of the registers by placing the result in this other register, wherein the content of that of the first and second registers which contains the multiplier of the operation of the first step is disturbed, for each bit of the exponent, during the execution of the first step.
Abstract translation: 一种验证在第一寄存器和第二寄存器中执行模幂运算的电子电路的灵敏度的方法，其连续地包括针对指数的每一位：第一步骤，将寄存器之一的内容从 根据指数的位的状态，通过第一和第二寄存器中的另一个的内容，将第一寄存器和第二寄存器置于所述寄存器的一个寄存器中; 通过将结果放置在该另一个寄存器中来平坦化所述另一个寄存器的内容的第二步骤，其中包含第一步骤的操作的乘法器的第一寄存器和第二寄存器的内容的内容被干扰 在执行第一步时，指数的位。
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公开(公告)号：US09582664B2
公开(公告)日：2017-02-28
申请号：US14299943
申请日：2014-06-09
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
CPC classification number: G06F21/55 , G06F7/58 , G06F21/556
Abstract: A method for detecting a fault injection in a random number generation circuit, wherein a bit pattern is mixed to a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mix.
Abstract translation: 一种用于检测随机数生成电路中的故障注入的方法，其中将位模式混合到源自噪声源的比特流，并且在混合下游采样的信号中检测到该模式的存在。
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公开(公告)号：US09311510B2
公开(公告)日：2016-04-12
申请号：US14848747
申请日：2015-09-09
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
IPC: G06F21/10 , H04N21/4405 , G06F21/79 , G06F21/56 , G06F12/14
CPC classification number: G06F21/6218 , G06F12/1425 , G06F12/1483 , G06F21/561 , G06F21/566 , G06F21/79 , G06F2212/1052 , G06F2221/034
Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.
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Patent Agency Ranking
公开(公告)号：US20150063561A1
公开(公告)日：2015-03-05
申请号：US14470861
申请日：2014-08-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
CPC classification number: H04L9/0618 , H04L9/002 , H04L9/003 , H04L9/0869 , H04L9/3066
Abstract: A method for protecting a ciphering algorithm executing looped operations on bits of a first quantity and on a first variable initialized by a second quantity, wherein, for each bit of the first quantity, a random number is added to the state of this bit to update a second variable maintained between two thresholds.
Abstract translation: 一种用于保护加密算法对第一数量的比特和由第二数量初始化的第一变量执行循环操作的方法，其中对于第一数量的每个比特，将随机数加到该比特的状态以更新 第二个变量保持在两个阈值之间。
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公开(公告)号：US10263768B2
公开(公告)日：2019-04-16
申请号：US15354016
申请日：2016-11-17
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
Abstract: A method for protecting a ciphering algorithm executing looped operations on bits of a first quantity and on a first variable initialized by a second quantity, wherein, for each bit of the first quantity, a random number is added to the state of this bit to update a second variable maintained between two thresholds.
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公开(公告)号：US20170286687A1
公开(公告)日：2017-10-05
申请号：US15622991
申请日：2017-06-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
CPC classification number: G06F21/575 , G01K13/00 , G06F12/1458 , G06F21/554 , G06F21/71 , G06F2212/1052 , G06F2221/034 , G06F2221/2137
Abstract: A method of detecting a cold-boot attack includes transferring, into a first volatile memory of an integrated circuit, a pattern stored in a non-volatile memory of the integrated circuit. Power to the non-volatile memory is periodically interrupted and an indication of a number of errors in the non-volatile memory is generated. The indication of the number of errors is compared to one or more thresholds. An occurrence of a cold-boot attack is detected based on the comparison. The pattern may be reloaded into the first volatile memory before each power interruption. The pattern may be selected so that the number of errors varies according to the integrated circuit temperature.
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公开(公告)号：US09767277B2
公开(公告)日：2017-09-19
申请号：US15405044
申请日：2017-01-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
CPC classification number: G06F21/55 , G06F7/58 , G06F21/556
Abstract: A method for detecting a fault injection in a circuit, wherein a bit pattern is mixed in a bit stream originating from a noise source and the presence of this pattern is detected in a signal sampled downstream of the mixing.
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公开(公告)号：US09563787B2
公开(公告)日：2017-02-07
申请号：US15060159
申请日：2016-03-03
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Yannick Teglia
CPC classification number: G06F21/6218 , G06F12/1425 , G06F12/1483 , G06F21/561 , G06F21/566 , G06F21/79 , G06F2212/1052 , G06F2221/034
Abstract: A method for protecting a volatile memory against a virus, wherein: rights of writing, reading, or execution are assigned to certain areas of the memory; and a first list of opcodes authorized or forbidden as a content of the areas is associated with each of these areas.
Abstract translation: 一种用于保护针对病毒的易失性存储器的方法，其中：写入，读取或执行的权限被分配给存储器的某些区域; 并且作为该区域的内容的授权或禁止的操作码的第一列表与这些区域中的每一个相关联。
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