公开(公告)号：US11429478B2

公开(公告)日：2022-08-30

申请号：US16867325

申请日：2020-05-05

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Jain

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/07 ,  G06F11/32 ,  G06F11/16

Abstract: A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.

公开(公告)号：US20200007129A1

公开(公告)日：2020-01-02

申请号：US16452051

申请日：2019-06-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Andrea Mario Veggetti ,  Abhishek Jain

IPC: H03K19/003 ,  H03K3/037 ,  H03K3/356 ,  G01R31/3181 ,  G11C7/10

Abstract: A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.

公开(公告)号：US09160336B2

公开(公告)日：2015-10-13

申请号：US13715721

申请日：2012-12-14

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Jain ,  Chittoor Parthasarathy ,  Kallol Chatterjee

IPC: G06F17/50 ,  H03K19/003

CPC classification number: H03K19/003 ,  G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

Abstract translation: 公开了一种用于在电路中提供关键路径复制系统的系统和方法。 通过确定电路中的关键路径，产生关键路径复制电路，生成电路蓝图以及创建蓝图电路来创建关键路径复制系统。 该电路包括具有功能逻辑元件的功能逻辑模块和具有逻辑元件的复制逻辑模块。 每个逻辑元件被配置为复制一个或多个功能逻辑元件并处理测试信号。 复制错误检测模块分析处理的信号以确定是否发生定时冲突。 在一些实施例中，副本逻辑模块还包括一个或多个加载模块。 复制控制器可以基于报告的错误来修改电路的操作。 复制模式选择模块将副本逻辑模块设置为老化测试模式或定时传感器模式。

公开(公告)号：US20150169394A1

公开(公告)日：2015-06-18

申请号：US14631128

申请日：2015-02-25

Applicant: STMicroelectronics International N.V.

Inventor： Chittoor Parthasarathy ,  Abhishek Jain

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/1608 ,  H03K3/0375

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

Abstract translation: 电路的实施例包括数据锁存器和多个级联锁存器，其中多个级联锁存器中的第一个锁存器被配置为从数据锁存器接收第一信号，并且每个后续级联锁存器被配置为接收数据锁存器的数据输出信号 一个先前的级联锁存器和一个错误检测电路，配置成接收相应的数据输出信号，并在此基础上检测级联锁存器工作中的错误。