公开(公告)号：US20240331768A1

公开(公告)日：2024-10-03

申请号：US18619699

申请日：2024-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Ashfaque AHMED

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: An electronic device includes a memory and includes a plurality of word lines selectively driven by a decoder, with each pair of adjacent word lines having an underdrive circuit coupled therebetween. That underdrive circuit includes first and second transistors source/drain coupled in series with one another between the pair of adjacent word lines, the first and second transistors being replicas of a pull-down transistor and a pass gate transistor of bitcells the memory. One of the first and second transistors has its gate driven by a supply voltage and the other of the first and second transistor has its gate driven by a first read assist control signal.

公开(公告)号：US20240170032A1

公开(公告)日：2024-05-23

申请号：US18389314

申请日：2023-11-14

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/106 ,  G11C7/1069 ,  G11C8/10

Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location in response to assertion of control signal having a dynamically variable delay dependent on the current data word. The operations are advantageously performed within a single clock cycle.