公开(公告)号：US20150268133A1

公开(公告)日：2015-09-24

申请号：US14218482

申请日：2014-03-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Om Ranjan ,  Giampiero Borgonovo ,  Deepak Baranwal

IPC: G01M99/00

CPC classification number: G06F11/0736 ,  G05B19/0428 ,  G05B23/0254 ,  G05B2219/2637 ,  G06F11/2205 ,  G06F11/3013

Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.

Abstract translation: 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。

公开(公告)号：US20210294534A1

公开(公告)日：2021-09-23

申请号：US17341054

申请日：2021-06-07

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Roberto Colombo ,  Om Ranjan

IPC: G06F3/06 ,  G06F13/36 ,  H04L9/06

Abstract: A processing system includes a plurality of configuration data clients, each associated with a respective address and including a respective register, and where a respective configuration data client is configured to receive a respective first configuration data and to store the respective first configuration data in the respective register; a hardware block coupled to at least one of the configuration data clients and configured to change operation as a function of the respective first configuration data stored in the respective registers; a non-volatile memory including second configuration data, where the second configuration data are stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients; and a hardware configuration circuit configured to sequentially read the data packets from the non-volatile memory and to transmit the respective first configuration data to the respective configuration data client.

公开(公告)号：US10528422B2

公开(公告)日：2020-01-07

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US20190146868A1

公开(公告)日：2019-05-16

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.