公开(公告)号：US11436162B2

公开(公告)日：2022-09-06

申请号：US16881949

申请日：2020-05-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Riccardo Gemelli ,  Denis Dutey ,  Om Ranjan

IPC: G06F12/14 ,  G06F11/07 ,  G06F13/40 ,  H04L9/40

Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.

公开(公告)号：US20200379924A1

公开(公告)日：2020-12-03

申请号：US16881949

申请日：2020-05-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Riccardo Gemelli ,  Denis Dutey ,  Om Ranjan

IPC: G06F12/14 ,  G06F13/40 ,  G06F11/07 ,  H04L29/06

Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.

公开(公告)号：US10379937B2

公开(公告)日：2019-08-13

申请号：US15798916

申请日：2017-10-31

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Abhishek Gupta

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

公开(公告)号：US11055173B2

公开(公告)日：2021-07-06

申请号：US16703672

申请日：2019-12-04

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US10860415B2

公开(公告)日：2020-12-08

申请号：US16454365

申请日：2019-06-27

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Abhishek Gupta

IPC: G06F11/00 ,  H04L1/00 ,  G06F11/10 ,  G06F3/06

Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

公开(公告)号：US09990245B2

公开(公告)日：2018-06-05

申请号：US14951639

申请日：2015-11-25

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Om Ranjan ,  Fabio Enrico Carlo Disegni

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/08 ,  G06F11/16 ,  G11C29/42 ,  G11C29/02 ,  G11B20/18 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1004 ,  G06F11/16 ,  G11B2020/1843 ,  G11C29/02 ,  G11C29/04 ,  G11C29/42

Abstract: An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.

公开(公告)号：US10528422B2

公开(公告)日：2020-01-07

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US20190146868A1

公开(公告)日：2019-05-16

申请号：US15810731

申请日：2017-11-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Denis Dutey

IPC: G06F11/10 ,  G11C29/52

Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

公开(公告)号：US20190129790A1

公开(公告)日：2019-05-02

申请号：US15798916

申请日：2017-10-31

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Om Ranjan ,  Riccardo Gemelli ,  Abhishek Gupta

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/10 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  H04L1/0045 ,  H04L1/0063 ,  H04L1/0082

Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

公开(公告)号：US20150268133A1

公开(公告)日：2015-09-24

申请号：US14218482

申请日：2014-03-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Om Ranjan ,  Giampiero Borgonovo ,  Deepak Baranwal

IPC: G01M99/00

CPC classification number: G06F11/0736 ,  G05B19/0428 ,  G05B23/0254 ,  G05B2219/2637 ,  G06F11/2205 ,  G06F11/3013

Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.

Abstract translation: 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。