公开(公告)号：US20210342277A1

公开(公告)日：2021-11-04

申请号：US17224772

申请日：2021-04-07

Applicant: STMicroelectronics S.r.l.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G06F13/16 ,  G06F7/523 ,  G06F7/50 ,  G06F13/40 ,  G06F13/28

Abstract: An embodiment circuit comprises a set of input terminals configured to receive input digital signals which carry input data, a set of output terminals configured to provide output digital signals which carry output data, and computing circuitry configured to produce the output data as a function of the input data. The computing circuitry comprises a set of multiplier circuits, a set of adder-subtractor circuits, a set of accumulator circuits, and a configurable interconnect network. The configurable interconnect network is configured to selectively couple the multiplier circuits, the adder-subtractor circuits, the accumulator circuits, the input terminals and the output terminals in at least two processing configurations. In a first configuration, the computing circuitry is configured to compute the output data according to a first set of functions, and, in a second configuration, the computing circuitry is configured to compute the output data according to a different set of functions.

公开(公告)号：US11742049B2

公开(公告)日：2023-08-29

申请号：US17453811

申请日：2021-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Giampiero Borgonovo ,  Lorenzo Re Fiorentin

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/4401

Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.

公开(公告)号：US11321492B2

公开(公告)日：2022-05-03

申请号：US17107183

申请日：2020-11-30

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio ,  Lorenzo Re Fiorentin

IPC: G06F9/448 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30 ,  G06F21/71 ,  G06F21/60 ,  H04L9/06 ,  G06F11/07 ,  G06F21/57 ,  G06F21/72 ,  G06F21/77 ,  H03K19/17728

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.