公开(公告)号：US20010036121A1

公开(公告)日：2001-11-01

申请号：US09773283

申请日：2001-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Nicosia ,  Fabrizio Campanale ,  Francesco Tomaiuolo ,  Luca Giuseppe De Ambroggi ,  Luigi Pascucci

IPC: G11C008/18

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.

Abstract translation: 基于外部产生的包括地址锁存使能信号和芯片使能信号的命令信号，交错存储器在顺序存取同步模式和随机存取异步模式下是可读的。 存储器包括用于再生外部产生的地址锁存使能信号的电路。 第一和第二内部复制信号由电路产生。 第二内部复制信号具有相对于第一内部副本信号的前沿被延迟的前沿。 第二内部副本信号的持续时间有条件地增加，以防止当交错存储器以顺序存取同步模式或随机存取异步模式运行时外部产生的地址锁存使能信号和外部产生的芯片使能信号之间的不同步 。