公开(公告)号：US09823965B2

公开(公告)日：2017-11-21

申请号：US15080307

申请日：2016-03-24

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Gaetano Di Stefano ,  Antonin Fried

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1044 ,  G11C29/52

Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.