Display device
    11.
    发明授权

    公开(公告)号:US11706954B2

    公开(公告)日:2023-07-18

    申请号:US17002113

    申请日:2020-08-25

    CPC classification number: H10K59/124 H10K59/122 H10K59/126 H10K59/1201

    Abstract: A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.

    Pixel of display device
    12.
    发明授权

    公开(公告)号:US11610541B1

    公开(公告)日:2023-03-21

    申请号:US17810031

    申请日:2022-06-30

    Abstract: A pixel includes a light emitting element, first through third transistors, sixth through seventh transistors, a ninth transistor, and a capacitor. The first transistor is connected between supply and a second node and controls a driving current supplied to the light emitting element. The second transistor is connected between a third node and a data line. The third transistor is connected between a first node connected to a gate electrode of the first transistor and the second node. The sixth transistor is connected between the supply and a fifth node connected to an electrode of the first transistor. The seventh transistor is connected between the second node and a fourth node connected to an anode of the light emitting element. The ninth transistor is connected between the fifth node and bias. Gate electrodes of the sixth through seventh transistors and the ninth transistor are connected to a same emission line.

    Display device
    13.
    发明授权

    公开(公告)号:US11355528B2

    公开(公告)日:2022-06-07

    申请号:US16890756

    申请日:2020-06-02

    Abstract: A display device includes: a bending region including a bending peripheral opening passing through the first interlayer insulating film and the first gate insulating film and a bending opening in the bending peripheral opening and passing through the second interlayer insulating film and the buffer layer to expose the substrate, a first sidewall of the bending peripheral opening includes a side surface of the first interlayer insulating film and a side surface of the first gate insulating film, the second interlayer insulating film covers the first sidewall of the bending peripheral opening, the bending opening includes a second sidewall including a side surface of the buffer layer and a portion of a side surface of the second interlayer insulating film arranged with the side surface of the buffer layer, and the first via layer fills the bending opening.

    DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE

    公开(公告)号:US20210143189A1

    公开(公告)日:2021-05-13

    申请号:US17036619

    申请日:2020-09-29

    Abstract: A display device includes a substrate, a first active layer on the substrate, a first insulation layer on the first active layer, a first gate electrode on the first insulation layer, the first gate electrode overlapping the first active layer, a second insulation layer on the first gate electrode, a second active layer on the second insulation layer, a first capacitor electrode on the second insulation layer, the first capacitor electrode overlapping the first gate electrode, a third insulation layer on the second active layer and the first capacitor electrode, a second gate electrode on the third insulation layer, the second gate electrode overlapping the second active layer, and a second capacitor electrode on the third insulation layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode.

    Transistor, thin film transistor array panel, and related manufacturing method

    公开(公告)号:US10580902B2

    公开(公告)日:2020-03-03

    申请号:US15691207

    申请日:2017-08-30

    Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.

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