公开(公告)号：US20180247603A1

公开(公告)日：2018-08-30

申请号：US15964249

申请日：2018-04-27

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Duc-han Cho ,  Beomjun Kim ,  Yoonho Kim ,  Noboru Takeuchi ,  Kangnam Kim

IPC: G09G3/36 ,  G11C19/28 ,  G11C19/18

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.

公开(公告)号：US20170287432A1

公开(公告)日：2017-10-05

申请号：US15470968

申请日：2017-03-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JIHEE YOON ,  Kang-woo Kim ,  Beomjun Kim ,  Jonghwan Lee ,  Hong-woo Lee

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3696 ,  G09G3/2074 ,  G09G3/3614 ,  G09G3/3659 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0852 ,  G09G2310/0205

Abstract: A display device includes a display panel having a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driving circuit that outputs a plurality of gate signals to the plurality of gate lines, and a data driving circuit configured that outputs a plurality of data signals for driving the plurality of data lines. Each of the plurality of pixels includes a first sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to a first gate signal among the plurality of gate signals, and a second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal among the plurality of gate signals. The second gate signal is a signal delayed by a 2×d×H time relative to the first gate signal (where each of d and H is a positive integer, H is a horizontal period, and d×H is a pulse width of first and second gate signals).

公开(公告)号：US09766504B2

公开(公告)日：2017-09-19

申请号：US14730922

申请日：2015-06-04

Applicant: Samsung Display Co., Ltd.

Inventor： Min Soo Kang ,  Beomjun Kim

IPC: G02F1/1333 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1335

CPC classification number: G02F1/1339 ,  G02F1/133512 ,  G02F1/136204 ,  G02F2001/133334

Abstract: A display device includes an array substrate, an opposite substrate, a printed circuit board, and a conductive member. The array substrate includes pixel electrodes. The opposite substrate faces the array substrate, is coupled with array substrate, and includes a light blocking layer disposed in a non-pixel area of the array substrate. The printed circuit board includes a ground terminal and output terminals to apply a driving signal to the array substrate through the output terminals. The conductive member electrically connects the light blocking layer to the ground terminal.