DISPLAY DEVICE INCLUDING PIXELS WITH STEM AND BRANCH PORTIONS

    公开(公告)号:US20190079325A1

    公开(公告)日:2019-03-14

    申请号:US15962304

    申请日:2018-04-25

    Abstract: A display device includes a substrate; and a red pixel electrode, a green pixel electrode, and a blue pixel electrode disposed on the substrate. Each of the red pixel electrode, the green pixel electrode, and the blue pixel electrode includes a transverse stem portion, a longitudinal stem portion, and a fine branch portion. An angle between the transverse stem portion and the fine branch portion of the red pixel electrode, an angle between the transverse stem portion and the fine branch portion of the green pixel electrode, and an angle between the transverse stem portion and the fine branch portion of the blue pixel electrode are different from each other.

    Display device
    12.
    发明授权

    公开(公告)号:US09659535B2

    公开(公告)日:2017-05-23

    申请号:US14160865

    申请日:2014-01-22

    Abstract: A display device includes a timing controller configured to generate an image signal including a pre-emphasis voltage, a data driver configured to generate a plurality of data signals based on the image signal, and provide information about whether the image signal is normally received or not to the timing controller, and a display panel configured to receive the plurality of data signals and display images corresponding to the received data signals, where when the data driver fails to normally receive the image signal, the timing controller increases a level of the pre-emphasis voltage.

    Transmitter and transceiver including the same

    公开(公告)号:US12206514B2

    公开(公告)日:2025-01-21

    申请号:US18128323

    申请日:2023-03-30

    Abstract: A transmitter includes a transmission controller which outputs original data through an original data lane, an encoder which encodes the original data into encoded data and outputs the encoded data through an encoded data lane, and a transmission driver which outputs the encoded data at a speed of M (M is a real number greater than 0) gigabits per second through a transmission and reception interface. The transmission driver provides a first clock signal corresponding to an output speed to the encoder, the encoder provides a second clock signal having a second frequency less than a first frequency of the first clock signal to the transmission controller, the transmission controller outputs the original data based on the second clock signal, and the encoder outputs the encoded data based on the first clock signal.

    Transceiver and method of driving the same

    公开(公告)号:US12126704B2

    公开(公告)日:2024-10-22

    申请号:US18208127

    申请日:2023-06-09

    CPC classification number: H04L7/0037

    Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1−1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1−1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.

    TRANSCEIVER AND METHOD OF DRIVING THE SAME
    17.
    发明公开

    公开(公告)号:US20230306893A1

    公开(公告)日:2023-09-28

    申请号:US17974125

    申请日:2022-10-26

    Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals each having a first voltage range to the first line and the second line in a first mode, and signals each having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The receiver includes a low-power driver which receives signals through the first line and the second line in an operating state of the first mode, and stops an operation thereof in the second mode, and a high-speed driver which receives signals through the first line and the second line in the second mode, and stops an operation thereof in the first mode.

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