公开(公告)号：US20230163763A1

公开(公告)日：2023-05-25

申请号：US17825622

申请日：2022-05-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jong Man BAE ,  Hyun Su KIM ,  Jun Dal KIM ,  Dong Won PARK ,  Young Suk JUNG

IPC: H03K19/0175 ,  H03K7/02 ,  H03K9/02

CPC classification number: H03K19/017545 ,  H03K7/02 ,  H03K9/02

Abstract: A transceiver includes a transmitter and a receiver coupled to each other through a first line and a second line. The transmitter transmits a first voltage signal of a second logic level or a fourth logic level, among a first logic level, the second logic level, a third logic level, and the fourth logic level, through the first line. The transmitter transmits a second voltage signal of the first logic level or the third logic level through the second line. The receiver generates an output signal having one of four values based on the first voltage signal and the second voltage signal.

公开(公告)号：US20220399986A1

公开(公告)日：2022-12-15

申请号：US17574860

申请日：2022-01-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hyun Su KIM ,  Dong Won PARK ,  Jun Dal KIM ,  Kyung Youl MIN ,  Jong Man BAE ,  Jun Yong SONG ,  Tae Young JIN

IPC: H04L7/00

Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.

公开(公告)号：US20220397931A1

公开(公告)日：2022-12-15

申请号：US17574077

申请日：2022-01-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Yong SONG ,  Jong Man BAE ,  Jun Dal KIM ,  Hyun Su KIM ,  Kyung Youl MIN ,  Dong Won PARK ,  Tae Young JIN

IPC: G06F1/08 ,  G06F1/10

Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.

公开(公告)号：US20190304397A1

公开(公告)日：2019-10-03

申请号：US16287499

申请日：2019-02-27

Applicant: Samsung Display Co., Ltd.

Inventor： Tae Gon IM ,  Myeong Su KIM ,  Bo Yeon KIM ,  Sun Koo KANG ,  Yong Bum KIM ,  Dong Won PARK ,  Jung Hwan CHO

IPC: G09G5/00 ,  G09G3/36 ,  G09G3/3275

Abstract: A display device includes a timing controller configured to supply a first set signal to a data control signal line in a first frequency mode, and to supply a second set signal and a data signal to the data control signal line in a second frequency mode that is different from the first frequency mode, a data driver configured to recover the data signal supplied to the data control signal line according to a signal recovery characteristic value, to generate a plurality of data voltages based on the recovered data signal, and to adjust the signal recover characteristic value based on the first set signal and the second set signal, and a display unit including a plurality of pixels that emit lights with gray scales corresponding to the plurality of data voltages

公开(公告)号：US20190147831A1

公开(公告)日：2019-05-16

申请号：US16045918

申请日：2018-07-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Han LEE ,  Myeong Su KIM ,  Sun Koo KANG ,  Bo Yeon KIM ,  Dong Won PARK ,  Tae Gon IM ,  Jung Hwan CHO

IPC: G09G5/00 ,  G09G3/36 ,  G09G3/3275

Abstract: A display device may include a timing controller, a data driver and a plurality of pixels. The timing controller supplies a clock training pattern over a data/clock signal line in a first time period, and supplies pixel/control data over the data/clock signal line in a second time period. The data driver generates a clock signal, using the clock training pattern, in the first period, and generate a plurality of data voltages based on the plurality of pixel data, using the clock signal, in the second period. The plurality of pixels receive the plurality of data voltages and emit corresponding light. During the second period, the data driver outputs a feedback signal to the timing controller indicating that the locking of the clock signal has failed. The timing controller re-supplies the clock training pattern in response to the feedback signal.