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公开(公告)号：US20170098420A1
公开(公告)日：2017-04-06
申请号：US15132547
申请日：2016-04-19
发明人： Sun Koo KANG , Tae Gon KIM , Kyung Ha KIM , Jae Han LEE
IPC分类号： G09G3/36 , H03K17/687 , H03K5/06 , H03K3/356
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0809 , G09G2310/0289 , G09G2310/0291 , G09G2320/0219 , G09G2320/0223 , G11C19/28 , G11C27/02 , H03K3/356 , H03K5/06 , H03K17/6871
摘要： A scan driver includes stages respectively located in channels, the stages outputting a sampling signal, corresponding to at least one clock signal, and a buffer unit including buffers respectively located between the stages and scan lines, the buffers each outputting a scan signal to an output terminal thereof, corresponding to the sampling signal supplied through an input terminal thereof where an ith (i is a natural number) buffer located in an ith channel is electrically coupled to at least one specific buffer located in another channel different from the ith channel.
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公开(公告)号：US20210398473A1
公开(公告)日：2021-12-23
申请号：US17166388
申请日：2021-02-03
发明人： Ik Hyun AHN , Sun Koo KANG , Cheol Min KIM , Ji Ye MOON , Ju Gon SEOK , Hyeon Uk WON
IPC分类号： G09G3/20 , G09G3/3275 , G09G5/10
摘要： A display device includes: a gray converter which adds compensation grays to input grays to provide output grays; a data driver which provides data voltages corresponding to the output grays; and a display panel which includes pixels which receives the data voltages, where the gray converter includes: a voltage domain converter which converts the input grays into conversion grays; and a compensation gray calculator which calculates the compensation grays based on the conversion grays.
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公开(公告)号：US20200312251A1
公开(公告)日：2020-10-01
申请号：US16797488
申请日：2020-02-21
发明人： Won Tae KIM , Sun Koo KANG
IPC分类号： G09G3/3291
摘要： A display panel includes: a plurality of pixels connected to a plurality of data lines and a peripheral area at the periphery of the display area; a first channel group including a plurality of first shared channels respectively connected to shared data lines among the data lines; a second channel group including a plurality of second shared channels respectively connected to the shared data lines; a first source driver connected to the first channel group, the first source driver being configured to supply data signals to the shared data lines through the first channel group; and a second source driver connected to the second channel group, the second source driver being configured to supply the data signals to the shared data lines through the second channel group, wherein the first channel group and the second channel group forms a pair to be commonly connected the shared data lines.
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公开(公告)号：US20190304397A1
公开(公告)日：2019-10-03
申请号：US16287499
申请日：2019-02-27
发明人： Tae Gon IM , Myeong Su KIM , Bo Yeon KIM , Sun Koo KANG , Yong Bum KIM , Dong Won PARK , Jung Hwan CHO
IPC分类号： G09G5/00 , G09G3/36 , G09G3/3275
摘要： A display device includes a timing controller configured to supply a first set signal to a data control signal line in a first frequency mode, and to supply a second set signal and a data signal to the data control signal line in a second frequency mode that is different from the first frequency mode, a data driver configured to recover the data signal supplied to the data control signal line according to a signal recovery characteristic value, to generate a plurality of data voltages based on the recovered data signal, and to adjust the signal recover characteristic value based on the first set signal and the second set signal, and a display unit including a plurality of pixels that emit lights with gray scales corresponding to the plurality of data voltages
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公开(公告)号：US20190147831A1
公开(公告)日：2019-05-16
申请号：US16045918
申请日：2018-07-26
发明人： Jae Han LEE , Myeong Su KIM , Sun Koo KANG , Bo Yeon KIM , Dong Won PARK , Tae Gon IM , Jung Hwan CHO
IPC分类号： G09G5/00 , G09G3/36 , G09G3/3275
摘要： A display device may include a timing controller, a data driver and a plurality of pixels. The timing controller supplies a clock training pattern over a data/clock signal line in a first time period, and supplies pixel/control data over the data/clock signal line in a second time period. The data driver generates a clock signal, using the clock training pattern, in the first period, and generate a plurality of data voltages based on the plurality of pixel data, using the clock signal, in the second period. The plurality of pixels receive the plurality of data voltages and emit corresponding light. During the second period, the data driver outputs a feedback signal to the timing controller indicating that the locking of the clock signal has failed. The timing controller re-supplies the clock training pattern in response to the feedback signal.
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