-
公开(公告)号：US20220277680A1
公开(公告)日：2022-09-01
申请号：US17460779
申请日：2021-08-30
发明人： SI DUK SUNG , Dae Sik LEE , Sang Hyun LEE , Myeong Su KIM
IPC分类号： G09G3/20
摘要： A display device includes a scale factor provider, a grayscale converter, and pixels. The scale factor provider calculates an n-th scale factor based on n-th input grayscales received during an n-th frame period. The grayscale converter calculates (n+p)th output grayscales by applying the n-th scale factor to (n+p)th input grayscales received during an (n+p)th frame period in a first mode. The pixels output light to display an image based on the (n+p)th output grayscales, where n is an integer greater than 0 and p is an integer greater than 1.
-
公开(公告)号：US20190304397A1
公开(公告)日：2019-10-03
申请号：US16287499
申请日：2019-02-27
发明人： Tae Gon IM , Myeong Su KIM , Bo Yeon KIM , Sun Koo KANG , Yong Bum KIM , Dong Won PARK , Jung Hwan CHO
IPC分类号： G09G5/00 , G09G3/36 , G09G3/3275
摘要： A display device includes a timing controller configured to supply a first set signal to a data control signal line in a first frequency mode, and to supply a second set signal and a data signal to the data control signal line in a second frequency mode that is different from the first frequency mode, a data driver configured to recover the data signal supplied to the data control signal line according to a signal recovery characteristic value, to generate a plurality of data voltages based on the recovered data signal, and to adjust the signal recover characteristic value based on the first set signal and the second set signal, and a display unit including a plurality of pixels that emit lights with gray scales corresponding to the plurality of data voltages
-
公开(公告)号：US20190147831A1
公开(公告)日：2019-05-16
申请号：US16045918
申请日：2018-07-26
发明人： Jae Han LEE , Myeong Su KIM , Sun Koo KANG , Bo Yeon KIM , Dong Won PARK , Tae Gon IM , Jung Hwan CHO
IPC分类号： G09G5/00 , G09G3/36 , G09G3/3275
摘要： A display device may include a timing controller, a data driver and a plurality of pixels. The timing controller supplies a clock training pattern over a data/clock signal line in a first time period, and supplies pixel/control data over the data/clock signal line in a second time period. The data driver generates a clock signal, using the clock training pattern, in the first period, and generate a plurality of data voltages based on the plurality of pixel data, using the clock signal, in the second period. The plurality of pixels receive the plurality of data voltages and emit corresponding light. During the second period, the data driver outputs a feedback signal to the timing controller indicating that the locking of the clock signal has failed. The timing controller re-supplies the clock training pattern in response to the feedback signal.
-
公开(公告)号：US20220020334A1
公开(公告)日：2022-01-20
申请号：US17185155
申请日：2021-02-25
发明人： Won Tae KIM , Myeong Su KIM , Bo Yeon KIM , Jae Han LEE , Whee Won LEE
IPC分类号： G09G3/3275 , G09G3/3225
摘要： A display device includes a display panel including a plurality of pixels connected to data lines and sensing lines, a data driver including a plurality of buffer amplifiers which supplies a first sensing voltage to the data lines during a first sensing period and a sensor which receives a first sensing signal from the pixels through the sensing lines during the first sensing period, and a global amplifier which supplies a second sensing voltage to the data lines during a second sensing period different from the first sensing period. The sensor receives a second sensing signal corresponding to the second sensing voltage from the pixels through the sensing lines during the second sensing period, and generates compensation data based on a difference value between the first sensing signal and the second sensing signal.
-
公开(公告)号：US20210142714A1
公开(公告)日：2021-05-13
申请号：US16917740
申请日：2020-06-30
发明人： Si Duk SUNG , Sang Hyun LEE , Myeong Su KIM
IPC分类号： G09G3/20
摘要： A display device may include a timing controller, a level shifter, a gate driver, and a display panel. The timing controller may generate a first on-clock signal, a first off-clock signal, and a first output control signal. The level shifter may generate a first-type gate clock signal. A rising edge of the first-type gate clock signal and a falling edge of the first-type gate clock signal may be respectively synchronized with a rising edge of the first on-clock signal and a falling edge of the first off-clock signal. The gate driver may output first-type gate signals based on the first-type gate clock signal. The display panel may include pixels. The pixels may emit lights in response to the first-type gate signals. The level shifter may partially block a pulse of the first-type gate clock signal based on the first output control signal to generate sub-pulses.
-
公开(公告)号：US20230378045A1
公开(公告)日：2023-11-23
申请号：US18230069
申请日：2023-08-03
发明人： BoYeon KIM , Whee-Won LEE , Myeong Su KIM , Sang Hyun LEE
IPC分类号： H01L23/498 , H01L23/00 , H10K59/131
CPC分类号： H01L23/49838 , H01L23/4985 , H01L24/16 , H10K59/131 , H01L2224/16225
摘要： A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.
-
公开(公告)号：US20220101799A1
公开(公告)日：2022-03-31
申请号：US17215670
申请日：2021-03-29
发明人： Whee Won LEE , Myeong Su KIM , Bo Yeon KIM , Won Tae KIM , Jae Han LEE
IPC分类号： G09G3/3291 , G09G3/3266
摘要： A display device includes: a display panel including a plurality of pixels; a source driver for outputting a target initialization voltage in an analog format to the pixels through sensing lines; and a timing controller for providing the source driver with a data control signal including packet information associated with the target initialization voltage. The packet information is in a digital format. The source driver includes a digital-analog converter which generates the target initialization voltage in the analog format, based on the packet information.
-
公开(公告)号：US20180122295A1
公开(公告)日：2018-05-03
申请号：US15791497
申请日：2017-10-24
发明人： Ga Na KIM , Whee Won LEE , Myeong Su KIM
IPC分类号： G09G3/20 , G09G3/3233 , G09G3/3275
CPC分类号： G09G3/2096 , G09G3/20 , G09G3/3225 , G09G3/3233 , G09G3/3275 , G09G2310/0275 , G09G2310/0289 , G09G2310/08 , G09G2330/021 , G09G2330/12 , G09G2370/08
摘要： A display device includes: a timing controller which receives image data including high logics and low logics from the outside; a data driver which generates a data signal, based on the image data; and pixels which emit light with a luminance corresponding to the data signal, where the data driver determines an error of the image data, based on a checksum included in the image data.
-
公开(公告)号：US20150206467A1
公开(公告)日：2015-07-23
申请号：US14293856
申请日：2014-06-02
发明人： Jae Ho CHOI , Sil Yi BANG , Jang Hyun YEO , Myeong Su KIM
IPC分类号： G09G3/20
CPC分类号： G09G5/003 , G09G3/2055 , G09G2340/0428
摘要： The inventive concept relates to a display device and a driving method thereof. A display device according to an exemplary embodiment of the inventive concept includes: a display panel including a plurality of pixels and a plurality of data lines; a data driver applying data voltages to the plurality of data lines; a signal controller controlling the data driver; and a graphic controller inputting an image signal that is dithered based on dithering patterns of one set to the signal controller, wherein the signal controller includes a dithering cycle detector configured to detect a dithering cycle which is a cycle in which the dithering patterns of one set are repeated, and a still image detector configured to determine whether a current frame is a frame displaying a still image or a frame displaying a motion picture image based on the dithering cycle and the image signal.
摘要翻译： 本发明的概念涉及显示装置及其驱动方法。 根据本发明构思的示例性实施例的显示装置包括：显示面板，包括多个像素和多个数据线; 将数据电压施加到所述多条数据线的数据驱动器; 控制数据驱动器的信号控制器; 以及图形控制器，其将基于一组抖动模式的抖动图像信号输入到所述信号控制器，其中所述信号控制器包括抖动周期检测器，所述抖动周期检测器被配置为检测抖动周期，所述抖动周期是其中一组的抖动模式 以及静止图像检测器，被配置为基于抖动周期和图像信号来确定当前帧是显示静止图像的帧还是显示运动图像图像的帧。
-
公开(公告)号：US20220108656A1
公开(公告)日：2022-04-07
申请号：US17381134
申请日：2021-07-20
发明人： Jae Hoon LEE , Myeong Su KIM , Jae Woo RYU
IPC分类号： G09G3/3233 , G09G3/3275 , G09G3/3266
摘要： A display device includes pixels connected to scan lines, sensing lines, readout lines, and data lines; a scan driver including stages to supply a scan signal and a sensing signal to the scan lines and the sensing lines; a data driver which supplies a data signal to the data lines; a timing controller which divides one frame into an active period including a scan period in which the data signal is supplied to the data lines and a display period in which the pixels emit light in response to the data signal, and a blank period including a sensing period in which electrical characteristics of the pixels are detected and a reset period in which the stages are reset; and a compensator which generates a compensation value for compensating for deterioration of the pixels based on sensing values provided from the readout lines during the sensing period.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.018 秒)
