公开(公告)号：US20240113715A1

公开(公告)日：2024-04-04

申请号：US17956912

申请日：2022-09-30

申请人： Crossbar, Inc.

发明人： Sung Hyun Jo

IPC分类号： H03K19/17768 ,  H03K19/0175 ,  H03K19/17784

CPC分类号： H03K19/17768 ,  H03K19/017545 ,  H03K19/17784

摘要： A physical unclonable function (PUF) can be implemented on a transistor of an integrated circuit device to generate PUF data. A potential difference is supplied across a gate insulator to induce a conductive breakdown in the gate insulator material. Location of the conductive breakdown within the gate insulator and in relation to the source node and drain node can be highly unpredictable, randomly resulting in a higher gate-source current or higher gate-drain current, respectively. The gate-source or gate-drain current can be measured and digitized to generate the PUF data value from the transistor. Moreover, PUF data values generated from multiple transistors can be highly non-correlated and useful for a random data sequence for cryptographic applications and other security applications.

公开(公告)号：US20240088883A1

公开(公告)日：2024-03-14

申请号：US18517024

申请日：2023-11-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Hua Wen

IPC分类号： H03K17/08 ,  H03F3/45 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K17/08 ,  H03F3/45269 ,  H03K19/017545 ,  H03K19/018557 ,  H03K5/24

摘要： A post-driver with low voltage operation and electrostatic discharge protection is provided. A post-driver structure includes a drive unit including a pull-up driver and a pull-down driver, a pad connected to an external resistance, and an output node connected between the pull-up driver and the pull-down driver. The output node is configured to connect to a comparator for impedance calibration of the drive unit. The post-driver structure also includes an operational amplifier connected to a first transistor and the pad in a closed loop configuration. The operational amplifier is further connected to a second transistor to form a current mirror circuit between the operational amplifier and the drive unit. The current mirror circuit replicates a voltage at the pad with a voltage at the output node for the impedance calibration.

公开(公告)号：US11664804B1

公开(公告)日：2023-05-30

申请号：US17585173

申请日：2022-01-26

申请人： Ryan J. Epstein

发明人： Ryan J. Epstein

IPC分类号： H03K19/017 ,  H03K19/0175 ,  H03K19/195 ,  H01L39/24 ,  H01L39/22 ,  H01L27/18

CPC分类号： H03K19/017545 ,  H01L27/18 ,  H01L39/223 ,  H01L39/2493 ,  H03K19/1958

摘要： Systems and methods are provided for coupling two qubits. A first persistent current qubit is fabricated with a first superconducting loop interrupted by a first Josephson junction isolated by a first inductor and a second inductor from a second Josephson junction. A second persistent current qubit is fabricated with a second superconducting loop interrupted by a third Josephson junction isolated by a third inductor and a fourth inductor from a fourth Josephson junction. Nodes defined by the Josephson junctions of the first qubit and their neighboring inductors are connected to corresponding nodes defined by the third Josephson junction and the third inductor via a first capacitor, with one pair of connections swapped such that the nodes are not connected to their respective corresponding nodes.

公开(公告)号：US10057090B2

公开(公告)日：2018-08-21

申请号：US15276515

申请日：2016-09-26

申请人： QUALCOMM Incorporated

发明人： Madjid Hafizi

IPC分类号： H04L25/03 ,  G05F1/56 ,  H03K19/0175

CPC分类号： H04L25/03885 ,  G05F1/56 ,  G06F2213/0042 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017545 ,  H04L25/03343

摘要： A transmit driver or transmitter is provided to generate an output data signal based on different input modes, such as low speed (LS), full speed (FS), high speed (HS), and high speed interconnect (HSIC) modes of a Universal Serial Bus (USB) standard. The transmit driver includes a rail voltage generator for generating a rail voltage for a set of transmit driver slices based on the selected mode. The transmit driver includes a bias voltage generator for generating a bias voltage based on the selected mode for protecting transistors in the transmit driver slices from over-voltage stress. The transmit driver includes a predriver and level shifter for generating input signals for the transmit driver slices to set the output impedance of the transmit driver and the slew rate of the output data signal. The transmit driver includes an emphasis equalizer for providing controllable emphasis equalization to the output data signal.

公开(公告)号：US20180091333A1

公开(公告)日：2018-03-29

申请号：US15276515

申请日：2016-09-26

申请人： QUALCOMM Incorporated

发明人： Madjid Hafizi

IPC分类号： H04L25/03

CPC分类号： H04L25/03885 ,  G05F1/56 ,  G06F2213/0042 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017545 ,  H04L25/03343

摘要： A transmit driver or transmitter is provided to generate an output data signal based on different input modes, such as low speed (LS), full speed (FS), high speed (HS), and high speed interconnect (HSIC) modes of a Universal Serial Bus (USB) standard. The transmit driver includes a rail voltage generator for generating a rail voltage for a set of transmit driver slices based on the selected mode. The transmit driver includes a bias voltage generator for generating a bias voltage based on the selected mode for protecting transistors in the transmit driver slices from over-voltage stress. The transmit driver includes a predriver and level shifter for generating input signals for the transmit driver slices to set the output impedance of the transmit driver and the slew rate of the output data signal. The transmit driver includes an emphasis equalizer for providing controllable emphasis equalization to the output data signal.

公开(公告)号：US20180062651A1

公开(公告)日：2018-03-01

申请号：US15402958

申请日：2017-01-10

申请人： SK hynix Inc.

发明人： Hae Kang JUNG

IPC分类号： H03K19/00 ,  H03K19/0175

CPC分类号： H03K19/0005 ,  H03K17/687 ,  H03K19/00384 ,  H03K19/017509 ,  H03K19/017545

摘要： A data transmission device may include a calibration circuit and an output driver. The calibration circuit may generate a pull-up calibration voltage and a pull-down calibration voltage. The resistance value of the output driver may be changed based on the pull-up calibration voltage and the pull-down calibration voltage.

公开(公告)号：US09871539B2

公开(公告)日：2018-01-16

申请号：US15069880

申请日：2016-03-14

申请人： MEDIATEK INC.

发明人： Chien-Hua Wu ,  Yan-Bin Luo

IPC分类号： H03B1/04 ,  H04L25/00 ,  H04B1/04 ,  H03K19/0185 ,  H04L25/02 ,  H03K19/0175

CPC分类号： H04B1/04 ,  H03K19/017545 ,  H03K19/018578 ,  H03K19/018585 ,  H04L25/00 ,  H04L25/0272

摘要： A driver circuit for receiving a data input and generating an output signal to a termination element according to at least the first data input is provided. The driver circuit includes a first output terminal, a current mode drive unit and a voltage mode drive unit. The current mode drive unit is arranged for selectively outputting a first reference current from the first output terminal to the termination element according to the first data input, and selectively receiving the first reference current through the first output terminal according to the first data input. The voltage mode drive unit is arranged for coupling one of a first reference voltage and a second reference voltage different from the second reference voltage to the first output terminal according to the first data input.

公开(公告)号：US09859869B1

公开(公告)日：2018-01-02

申请号：US15443343

申请日：2017-02-27

申请人： SK hynix Inc.

发明人： Kwang Hun Lee

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03H11/28 ,  H03K17/687

CPC分类号： H03H11/28 ,  H03K17/6872 ,  H03K19/0005 ,  H03K19/017545

摘要： A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may generate a calibration code by performing an impedance calibration operation, and may generate a correction calibration code by inverting or maintaining logic levels of the calibration code based on the calibration code. The output circuit may generate an output signal based on an input signal and the correction calibration code.

公开(公告)号：US20170353184A1

公开(公告)日：2017-12-07

申请号：US15629265

申请日：2017-06-21

申请人： Rambus Inc.

发明人： Ian Shaeffer

IPC分类号： H03K19/00 ,  G11C16/06 ,  G11C11/4063 ,  G11C5/06 ,  G11C7/10 ,  G11C5/14 ,  H03K19/0175 ,  G11C11/413

CPC分类号： H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

摘要： Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

公开(公告)号：US20170288634A1

公开(公告)日：2017-10-05

申请号：US15408730

申请日：2017-01-18

申请人： DAE-WOON KANG ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Young-Don CHOI

发明人： DAE-WOON KANG ,  Jeong-Don IHM ,  Byung-Hoon JEONG ,  Young-Don CHOI

IPC分类号： H03H7/38 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC分类号： H03H7/38 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/105 ,  H03K19/0005 ,  H03K19/017545

摘要： A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.