公开(公告)号：US20230047588A1

公开(公告)日：2023-02-16

申请号：US17971297

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US11493850B2

公开(公告)日：2022-11-08

申请号：US16593149

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US09612528B2

公开(公告)日：2017-04-04

申请号：US14736706

申请日：2015-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Munja Kim ,  Byunggook Kim ,  Jaehyuck Choi

IPC: G03F1/62 ,  G03F1/64

CPC classification number: G03F1/62 ,  G03F1/64

Abstract: Provided is a method of manufacturing a pellicle. The method includes preparing a substrate, forming a membrane on the substrate by performing a chemical vapor deposition (CVD) process, separating the membrane from the substrate in a first solvent, rinsing the separated membrane in a second solvent, and transferring the separated membrane to a frame in a third solvent.

公开(公告)号：US20140302428A1

公开(公告)日：2014-10-09

申请号：US14095090

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： So-Eun Shin ,  Byunggook Kim ,  Jihyeon Choi

IPC: G03F1/80

CPC classification number: G03F1/80

Abstract: A photo-mask for fabricating a semiconductor device may include a transparent substrate including a main region, a supplementary region adjacent to the main region, a main pattern for developing circuits in a semiconductor device provided on the main region of the transparent substrate, and a supplementary pattern for optical proximity correction provided on the supplementary region of the transparent substrate. The main pattern has a sidewall perpendicular to a surface of the transparent substrate, and the supplementary pattern has a sidewall inclined to the surface of the transparent substrate and an upward tapered structure.

Abstract translation: 用于制造半导体器件的光掩模可以包括：透明基板，包括主区域，与主区域相邻的补充区域，设置在透明基板的主区域上的半导体器件中的显影电路的主图案，以及 在透明基板的辅助区域上设置用于光学邻近校正的补充图案。 主图案具有垂直于透明基板的表面的侧壁，辅助图案具有朝向透明基板的表面倾斜的侧壁和向上的锥形结构。