公开(公告)号：US10141286B2

公开(公告)日：2018-11-27

申请号：US15499229

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Il Lee ,  Cha-Jea Jo ,  Ji-Hwang Kim

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/02

Abstract: Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.

公开(公告)号：US09997446B2

公开(公告)日：2018-06-12

申请号：US15468294

申请日：2017-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hwang Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Won-Il Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.