公开(公告)号：US20140291854A1

公开(公告)日：2014-10-02

申请号：US14041169

申请日：2013-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teak-Hoon Lee ,  Ji-Hwang Kim ,  Sang-Wook Park ,  Young-Kun Jee

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through the adhesive layer and are connected to the TSVs and the active layer. Side surfaces of the adhesive layer are aligned with side surfaces of the second semiconductor chip.

Abstract translation: 半导体封装包括在衬底上的第一半导体芯片，并且具有多个穿硅通孔（TSV）。 具有有源层的第二半导体芯片在第一半导体芯片上。 粘合剂层位于第一半导体芯片和有源层之间。 连接端子延伸穿过粘合剂层并连接到TSV和有源层。 粘合剂层的侧表面与第二半导体芯片的侧表面对齐。

公开(公告)号：US10750112B2

公开(公告)日：2020-08-18

申请号：US16129010

申请日：2018-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hwang Kim ,  Hyo-Eun Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Sang-Uk Han

IPC: H04N5/369 ,  H04N5/225 ,  G02B5/20 ,  H01L27/146

Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.

公开(公告)号：US10199319B2

公开(公告)日：2019-02-05

申请号：US15485794

申请日：2017-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Bo Shim ,  Sang-Uk Han ,  Yun-Seok Choi ,  Ji-Hwang Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.

公开(公告)号：US08912048B2

公开(公告)日：2014-12-16

申请号：US13803662

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Youn Kim ,  Ji-Hwang Kim ,  Hae-Jung Yu ,  Cha-Jea Jo

IPC: H01L21/00 ,  H01L21/82

CPC classification number: H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10523 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/32225 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.

Abstract translation: 制造半导体器件的方法包括：使用载体固定层将半导体衬底附着到载体上，其中半导体衬底包括多个半导体芯片。 该方法还包括在相邻芯片之间形成间隙。 可以使用一种或多种化学品或光来形成间隙，所述化学物质或光用于去除半导体衬底的部分以暴露载体固定层。 然后移除载体固定层的附加部分以允许将芯片从载体上移除。

公开(公告)号：US10224272B2

公开(公告)日：2019-03-05

申请号：US16004539

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hwang Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Won-Il Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

公开(公告)号：US10141286B2

公开(公告)日：2018-11-27

申请号：US15499229

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Il Lee ,  Cha-Jea Jo ,  Ji-Hwang Kim

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L21/02

Abstract: Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.

公开(公告)号：US09997446B2

公开(公告)日：2018-06-12

申请号：US15468294

申请日：2017-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hwang Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Won-Il Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

公开(公告)号：US09159651B2

公开(公告)日：2015-10-13

申请号：US14041169

申请日：2013-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teak-Hoon Lee ,  Ji-Hwang Kim ,  Sang-Wook Park ,  Young-Kun Jee

IPC: H01L23/40 ,  H01L23/52 ,  H01L29/40 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: A semiconductor package includes a first semiconductor chip on a substrate and having a plurality of through-silicon vias (TSVs). A second semiconductor chip having an active layer is on the first semiconductor chip. An adhesive layer is between the first semiconductor chip and the active layer. Connection terminals extend through the adhesive layer and are connected to the TSVs and the active layer. Side surfaces of the adhesive layer are aligned with side surfaces of the second semiconductor chip.

Abstract translation: 半导体封装包括在衬底上的第一半导体芯片，并且具有多个通硅通孔（TSV）。 具有有源层的第二半导体芯片在第一半导体芯片上。 粘合剂层位于第一半导体芯片和有源层之间。 连接端子延伸穿过粘合剂层并连接到TSV和有源层。 粘合剂层的侧表面与第二半导体芯片的侧表面对齐。