公开(公告)号：US20240055403A1

公开(公告)日：2024-02-15

申请号：US18136499

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changeun Joo ,  Ohguk Kwon ,  Sunjae Kim

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/5383 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L2225/06568 ,  H01L2224/32145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/73253

Abstract: A semiconductor package may include a first redistribution substrate, a second redistribution substrate on the first redistribution substrate, a chip stack between the first redistribution substrate and the second redistribution substrate, a first molding layer on the chip stack, and a through electrode extending into the first molding layer and electrically connecting the first redistribution substrate to the second redistribution substrate. The chip stack may include a first semiconductor chip on the first redistribution substrate, the first semiconductor chip including a through via that extends therein, a chip structure including a second semiconductor chip and a second molding layer, the second semiconductor chip being on the first semiconductor chip and electrically connected to the through via, and a third semiconductor chip between the chip structure and the second redistribution substrate, and a side surface of the first semiconductor chip may be coplanar with a side surface of the chip structure.

公开(公告)号：US11810864B2

公开(公告)日：2023-11-07

申请号：US17849938

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changeun Joo ,  Gyujin Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L23/5383 ,  H01L21/565

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.