公开(公告)号：US20180158669A1

公开(公告)日：2018-06-07

申请号：US15886372

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Sic Yoon ,  Ki Seok Lee ,  Dong Oh Kim ,  Yong Jae Kim

IPC: H01L21/027 ,  H01L21/02 ,  G03F1/38

CPC classification number: H01L21/027 ,  G03F1/38 ,  H01L21/02107 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/10888

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, fowling a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

公开(公告)号：US11895833B2

公开(公告)日：2024-02-06

申请号：US17406418

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Oh Kim ,  Gyu Hyun Kil ,  Jung Hoon Han ,  Doo San Back

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

公开(公告)号：US20200295013A1

公开(公告)日：2020-09-17

申请号：US16890456

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook Jung ,  Dong Oh Kim ,  Seok Han Park ,  Chan Sic Yoon ,  Ki Seok Lee ,  Ho In Lee ,  Ju Yeon Jang ,  Je Min Park ,  Jin Woo Hong

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238 ,  H01L23/535

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US09916979B2

公开(公告)日：2018-03-13

申请号：US15381135

申请日：2016-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Sic Yoon ,  Ki Seok Lee ,  Dong Oh Kim ,  Yong Jae Kim

IPC: H01L21/02 ,  H01L21/027 ,  G03F1/38

CPC classification number: H01L21/027 ,  G03F1/38 ,  H01L21/02107 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/10888

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.