公开(公告)号：US10204919B2

公开(公告)日：2019-02-12

申请号：US15252740

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Il Lee ,  Joong Shik Shin ,  Dong Seog Eun ,  Kyung Jun Shin ,  Hyun Kook Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/02 ,  H01L27/11565

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

公开(公告)号：US10153292B2

公开(公告)日：2018-12-11

申请号：US15907667

申请日：2018-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  Hanmei Choi

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L49/02

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.