公开(公告)号：US10546874B2

公开(公告)日：2020-01-28

申请号：US15841523

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: G11C8/00 ,  H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US09716104B2

公开(公告)日：2017-07-25

申请号：US14987835

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  HanMei Choi

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11568

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US10854631B2

公开(公告)日：2020-12-01

申请号：US16719089

申请日：2019-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  G11C7/14 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US09972636B2

公开(公告)日：2018-05-15

申请号：US15626395

申请日：2017-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  Hanmei Choi

IPC: H01L27/115 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/04

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US10964720B2

公开(公告)日：2021-03-30

申请号：US17028047

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Kwang Young Jung ,  Dong Seog Eun

IPC: H01L27/11582 ,  G11C11/4099 ,  H01L27/11526 ,  H01L27/11565 ,  G11C16/10 ,  H01L27/11575 ,  H01L27/1157 ,  G11C7/14

Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.

公开(公告)号：US10103165B2

公开(公告)日：2018-10-16

申请号：US15481609

申请日：2017-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Hwan Son ,  Won Chul Jang ,  Dong Seog Eun ,  Jae Hoon Jang

IPC: H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.

公开(公告)号：US09773806B1

公开(公告)日：2017-09-26

申请号：US15390977

申请日：2016-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Il Lee ,  Kyung Jun Shin ,  Dong Seog Eun ,  Ji Hye Kim ,  Hyun Kook Lee

IPC: H01L21/8239 ,  H01L27/115 ,  H01L27/11582 ,  H01L27/11568 ,  G11C16/24 ,  G11C16/04 ,  H01L21/8238

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/823885 ,  H01L21/8239 ,  H01L27/1157

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.

公开(公告)号：US11716849B2

公开(公告)日：2023-08-01

申请号：US17143216

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Yong Chung ,  Ho Jin Kim ,  Young-Jin Kwon ,  Dong Seog Eun

IPC: H01L27/11582 ,  H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

公开(公告)号：US20190115366A1

公开(公告)日：2019-04-18

申请号：US16212240

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYOUNG IL LEE ,  Joong Shik Shin ,  Dong Seog Eun ,  Kyung Jun Shin ,  Hyun Kook Lee

IPC: H01L27/11582 ,  H01L27/02 ,  H01L27/11565

Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

公开(公告)号：US10211220B2

公开(公告)日：2019-02-19

申请号：US15688011

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Il Lee ,  Kyung Jun Shin ,  Dong Seog Eun ,  Ji Hye Kim ,  Hyun Kook Lee

IPC: H01L27/115 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/1157 ,  H01L21/8239 ,  H01L21/8238 ,  H01L27/11568

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.