Abstract:
A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.
Abstract:
A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.
Abstract:
An endecryptor and a control device are provided. The endecryptor includes a first SBOX configured to replace first input data with first substitution data, a transformation unit configured to replace the first input data with second substitution data and an output terminal configured to output encrypted or decrypted output data based on the first and second substitution data.
Abstract:
A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.
Abstract:
A host controller that controls a storage device includes an encryption unit that is selectively configured in response to file encryption information and disk encryption information to encrypt data. The encryption unit encrypts the data using a file encryption operation based on the file encryption information and/or a disk encryption operation based on the disk encryption information.
Abstract:
A method for encryption, decryption, or encryption and decryption of data in a crypto device having at least one crypto core may include: generating a tweak value corresponding to block data, which is placed at a random position from which the encryption, decryption, or encryption and decryption starts, from among sequential block data; and/or performing the encryption, decryption, or encryption and decryption from the block data using the tweak value. A method for encryption, decryption, or encryption and decryption of block data may include: generating a tweak value corresponding to the block data at a random position; and/or performing the encryption, decryption, or encryption and decryption of the block data using the tweak value.
Abstract:
Generating a random permutation by arranging a sequence N numbers in a matrix, performing random arrangement operations on the rows of the matrix to generate an intermediary matrix, performing random arrangement operations on the columns of the intermediary matrix to generate a second intermediary matrix, and arranging the N numbers of the second intermediary matrix as a rearranged sequence of the N numbers.