ENDECRYPTOR PREVENTING SIDE CHANNEL ATTACK, DRIVING METHOD THEREOF AND CONTROL DEVICE HAVING THE SAME
    1.
    发明申请
    ENDECRYPTOR PREVENTING SIDE CHANNEL ATTACK, DRIVING METHOD THEREOF AND CONTROL DEVICE HAVING THE SAME 审中-公开
    防止侧面通道攻击的防护装置及其驱动方法及其控制装置

    公开(公告)号:US20160065361A1

    公开(公告)日:2016-03-03

    申请号:US14746976

    申请日:2015-06-23

    CPC classification number: H04L9/002 H04L9/0631 H04L2209/24 H04L2209/34

    Abstract: An endecryptor and a control device are provided. The endecryptor includes a first SBOX configured to replace first input data with first substitution data, a transformation unit configured to replace the first input data with second substitution data and an output terminal configured to output encrypted or decrypted output data based on the first and second substitution data.

    Abstract translation: 提供了一个封装和控制装置。 所述封堵器包括配置成用第一替代数据替换第一输入数据的第一SBOX,被配置为用第二替代数据替换第一输入数据的变换单元和被配置为基于第一和第二替换来输出加密或解密的输出数据的输出端 数据。

    STORAGE DEVICE, AUTHENTICATION DEVICE, AND AUTHENTICATION SYSTEM

    公开(公告)号:US20250077096A1

    公开(公告)日:2025-03-06

    申请号:US18430315

    申请日:2024-02-01

    Abstract: A storage device includes: authentication device for receiving a certificate generated based on a first private key that corresponds to a first public key, the first public key, and a second public key from a debugging device, authenticating the first public key, authenticating the second public key when the authentication of the first public key is successful, and outputting a debugging enable signal when the authentication of the second public key is successful; a processor for receiving a debugging signal from the debugging device in response to the debugging enable signal, and performing debugging based on the debugging signal.

    Storage device, operating method for the same and memory system

    公开(公告)号:US11977447B2

    公开(公告)日:2024-05-07

    申请号:US17742164

    申请日:2022-05-11

    CPC classification number: G06F11/1428 G06F2201/805

    Abstract: A storage device with improved security performance is provided. The storage device comprises a first non-volatile memory storing a firmware image, a second non-volatile memory storing an emergency image, and a storage controller controlling the first and second non-volatile memories, wherein the storage controller checks an integrity of the firmware image received from the first non-volatile memory, loads and executes the emergency image from the second non-volatile memory when the integrity check of the firmware image fails, receives a recover image from an external device based on the emergency image, and provides the recover image to the first non-volatile memory.

    Electronic system having integrity verification device

    公开(公告)号:US09703960B2

    公开(公告)日:2017-07-11

    申请号:US14638862

    申请日:2015-03-04

    Abstract: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation. The electronic system includes: a memory device; a processor configured to provide a plurality of configuration records corresponding to a plurality of verification data stored in the memory device, each of the configuration records including a start address, a data length, and a reference hash value for a corresponding verification data; and an integrity verification device configured to: store the configuration records, select a configuration record, directly access the memory device to read verification data, corresponding to the selected configuration record, based on the start address and the data length included in the selected configuration record, perform a hash operation on the verification data to obtain a verification hash value, and output an interrupt signal based on the verification hash value and the reference hash value comprised in the selected configuration record.

    Electronic system having integrity verification device

    公开(公告)号:US10289849B2

    公开(公告)日:2019-05-14

    申请号:US15636814

    申请日:2017-06-29

    Abstract: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation. The electronic system includes: a memory device; a processor configured to provide a plurality of configuration records corresponding to a plurality of verification data stored in the memory device, each of the configuration records including a start address, a data length, and a reference hash value for a corresponding verification data; and an integrity verification device configured to: store the configuration records, select a configuration record, directly access the memory device to read verification data, corresponding to the selected configuration record, based on the start address and the data length included in the selected configuration record, perform a hash operation on the verification data to obtain a verification hash value, and output an interrupt signal based on the verification hash value and the reference hash value comprised in the selected configuration record.

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