公开(公告)号：US20190363088A1

公开(公告)日：2019-11-28

申请号：US16532857

申请日：2019-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In RYU ,  Taiheui CHO ,  Keunnam KIM ,  Kyehee YEOM ,  Junghwan PARK ,  Hyeon-Woo JANG

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US20160043171A1

公开(公告)日：2016-02-11

申请号：US14604339

申请日：2015-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo JANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L29/0653 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device. The semiconductor device includes an isolation region disposed in a semiconductor substrate and configured to define an active region. A gate electrode buried in the active region is disposed. A gate dielectric layer is disposed between the active region and the gate electrode. A first source/drain region and a second source/drain region are disposed in the active region on both sides of the gate electrodes. An interconnection structure intersecting with the gate electrode, overlapping the first and second source/drain regions, electrically connected with the first source/drain region, and spaced apart from the second source/drain region is disposed. A contact structure is disposed on the second source/drain region.

Abstract translation: 提供一种半导体器件。 半导体器件包括设置在半导体衬底中并被配置为限定有源区的隔离区。 设置埋在有源区中的栅电极。 栅介质层设置在有源区和栅电极之间。 第一源极/漏极区域和第二源极/漏极区域设置在栅电极两侧的有源区域中。 设置与栅电极相交的与第一和第二源极/漏极区重叠的互连结构，与第一源极/漏极区电连接并且与第二源极/漏极区域间隔开。 接触结构设置在第二源极/漏极区域上。