公开(公告)号：US20250142813A1

公开(公告)日：2025-05-01

申请号：US18648797

申请日：2024-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo Ho SHIN ,  Ji Hoon CHANG ,  Ga Eun LEE ,  Hyeon-Woo JANG

IPC: H10B12/00 ,  H01L23/528 ,  H01L29/51

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area defined around the cell area, a peripheral gate on the peripheral area and including a peripheral gate conductive film, peripheral wiring lines on the peripheral gate, peripheral wiring capping films respectively in contact with the peripheral wiring lines, wherein each peripheral wiring capping film includes upper and lower surfaces, and a peripheral wiring isolation pattern isolating adjacent peripheral wiring lines, and contacting a sidewall of the peripheral wiring lines, wherein the lower surface of each peripheral wiring capping film faces the substrate and contacts an upper surface of the peripheral wiring extension line, wherein a height from an upper surface of the substrate to the upper surface of each peripheral wiring extension line is smaller than a height from the upper surface of the substrate to an upper surface of the peripheral wiring isolation pattern.

公开(公告)号：US20240306380A1

公开(公告)日：2024-09-12

申请号：US18663550

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo JANG ,  Soo Ho SHIN

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the peri contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug.

公开(公告)号：US20130264638A1

公开(公告)日：2013-10-10

申请号：US13767992

申请日：2013-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Woo JANG ,  Won-Chul LEE ,  Jin-Won JEONG

IPC: H01L23/538 ,  H01L27/088

CPC classification number: H01L23/5384 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/10879 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulating layer on a substrate, and a direct contact (DC) structure vertically penetrating the interlayer insulating layer and contacting the substrate, the DC structure including a DC hole exposing the substrate, an insulating DC spacer on an inner wall of the DC hole, and a conductive DC plug on the DC spacer and filling the DC hole, the DC plug including a lower DC plug and an upper DC plug on the lower DC plug, the lower DC plug having a smaller horizontal width than that of the upper DC plug.

Abstract translation: 半导体器件包括在基板上的层间绝缘层和垂直穿过层间绝缘层并与基板接触的直接接触（DC）结构，包括露出基板的DC孔的DC结构，内壁上的绝缘DC间隔物 DC直流插头和直流隔离件上的导电直流插头，并填充直流孔，直流插头包括下直流插头的下部直流插头和上部直流插头，下部直流插头的水平宽度小于 的上部直流插头。

公开(公告)号：US20230189504A1

公开(公告)日：2023-06-15

申请号：US17953401

申请日：2022-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keon Hee PARK ,  Soo Ho SHIN ,  Hyeon-Woo JANG ,  Dong-Sik PARK ,  Ga Eun LEE

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor memory device includes a landing pad on a substrate, a lower electrode on and connected to the landing pad, a dielectric layer on and extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode, the upper plate electrode including a first sub-plate electrode and a second sub-plate electrode doped with boron, a first concentration of the boron in the first sub-plate electrode being greater than a second concentration of the boron in the second sub-plate electrode.

公开(公告)号：US20220189966A1

公开(公告)日：2022-06-16

申请号：US17368130

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo JANG ,  Soo Ho SHIN

IPC: H01L27/108

Abstract: A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the pen contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug.

公开(公告)号：US20200312852A1

公开(公告)日：2020-10-01

申请号：US16902338

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In RYU ,  Taiheui CHO ,  Keunnam KIM ,  Kyehee YEOM ,  Junghwan PARK ,  Hyeon-Woo JANG

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US20230043650A1

公开(公告)日：2023-02-09

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20210305153A1

公开(公告)日：2021-09-30

申请号：US17153963

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20140110851A1

公开(公告)日：2014-04-24

申请号：US14045648

申请日：2013-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam KIM ,  Sun-Young PARK ,  Soo-Ho SHIN ,  Kye-Hee YEOM ,  Hyeon-Woo JANG ,  Jin-Won JEONG ,  Chang-Hyun CHO ,  Hyeong-sun HONG

IPC: H01L23/48

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US20230039149A1

公开(公告)日：2023-02-09

申请号：US17747423

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan KIM ,  Keonhee PARK ,  Dong-Sik PARK ,  Joonsuk PARK ,  Jihoon CHANG ,  Hyeon-Woo JANG

IPC: H01L27/108 ,  H01L21/3213

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including a peripheral block and cell blocks each including a cell center region, a cell edge region, and a cell middle region, and bit lines extending on each cell block in a first direction. The bit lines include center bit lines, middle bit lines, and edge bit lines. The bit line has first and second lateral surfaces opposite to each other in a second direction. The first lateral surface straightly extends along the first direction on the cell center region, the cell middle region, and the cell edge region. The second lateral surface straightly extends along the first direction on the cell center region and the cell edge region, and the second lateral surface extends along a third direction, that intersects the first direction and the second direction, on the cell middle region.