公开(公告)号：US11011516B2

公开(公告)日：2021-05-18

申请号：US16705799

申请日：2019-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-han Lee ,  Sun-ghil Lee ,  Myung-il Kang ,  Jeong-yun Lee ,  Seung-hun Lee ,  Hyun-jung Lee ,  Sun-wook Kim

IPC: H01L27/088 ,  H01L27/11 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

公开(公告)号：US10672764B2

公开(公告)日：2020-06-02

申请号：US16174894

申请日：2018-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Dong-myoung Kim ,  Jin-bum Kim ,  Seung-hun Lee ,  Cho-eun Lee ,  Hyun-jung Lee ,  Sung-uk Jang ,  Edward Namkyu Cho ,  Min-hee Choi

IPC: H01L27/085 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.

公开(公告)号：US20190252376A1

公开(公告)日：2019-08-15

申请号：US16174894

申请日：2018-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Dong-myoung Kim ,  Jin-bum Kim ,  Seung-hun Lee ,  Cho-eun Lee ,  Hyun-jung Lee ,  Sung-uk Jang ,  Edward Namkyu Cho ,  Min-hee Choi

IPC: H01L27/085 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.

公开(公告)号：US20190027480A1

公开(公告)日：2019-01-24

申请号：US15920628

申请日：2018-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L27/108

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.