DISPLAY DRIVER INTEGRATED CIRCUIT AND DRIVING METHOD

    公开(公告)号:US20220013069A1

    公开(公告)日:2022-01-13

    申请号:US17208206

    申请日:2021-03-22

    Abstract: A display driver integrated circuit includes a first memory, a compensator, an accumulator and a second memory. The first memory stores a plurality of compensation data that are used to compensate for deterioration of a plurality of pixels. The compensator generates a plurality of output image data for image display by compensating a plurality of input image data based on the plurality of compensation data. The accumulator groups the plurality of pixels into a plurality of blocks, generates a plurality of block image data by sampling the plurality of output image data in block units, generates a plurality of block accumulation data in block units based on the plurality of block image data, and generates a plurality of pixel accumulation data in pixel units by synthesizing portions of the plurality of output image data and portions of the plurality of block accumulation data. The second memory stores the plurality of block accumulation data in a first period. The plurality of pixel accumulation data may be stored in a third memory in a second period longer than the first period.

    DISPLAY DRIVING CIRCUIT, DISPLAY DEVICE, AND DISPLAY SYSTEM

    公开(公告)号:US20240404455A1

    公开(公告)日:2024-12-05

    申请号:US18670839

    申请日:2024-05-22

    Abstract: A display device including a host interface circuit configured to receive first frame data through a first signal channel and second frame data through a second signal channel, a pixel array including a plurality of pixels, and a plurality of gate lines and a plurality of source lines connected to the plurality of pixels, and an image processing circuit configured to process the first frame data and the second frame data such that the pixel array displays one image including a first area rendered with a first quality and a second area rendered with a second quality that is different from the first quality during one frame period.

    RECEIVER AND METHOD FOR CONTROLLING EQUALIZATION

    公开(公告)号:US20240235903A9

    公开(公告)日:2024-07-11

    申请号:US18237638

    申请日:2023-08-24

    CPC classification number: H04L25/03267 H04L25/03878

    Abstract: A receiver includes a first equalizer that receives an input data signal through a communication channel and equalizes the input data signal based on a first control code to generate a first equalization signal, a second equalizer that equalizes the first equalization signal based on a clock signal and a second control code to generate a second equalization signal, a clock data recovery circuit that restores the clock signal based on the second equalization signal, deserializes the second equalization signal, and outputs a deserialized second equalization signal, and a controller that adjusts the first control code and the second control code based on the deserialized second equalization signal.

    RECEIVER AND METHOD FOR CONTROLLING EQUALIZATION

    公开(公告)号:US20240137251A1

    公开(公告)日:2024-04-25

    申请号:US18237638

    申请日:2023-08-23

    CPC classification number: H04L25/03267 H04L25/03878

    Abstract: A receiver includes a first equalizer that receives an input data signal through a communication channel and equalizes the input data signal based on a first control code to generate a first equalization signal, a second equalizer that equalizes the first equalization signal based on a clock signal and a second control code to generate a second equalization signal, a clock data recovery circuit that restores the clock signal based on the second equalization signal, deserializes the second equalization signal, and outputs a deserialized second equalization signal, and a controller that adjusts the first control code and the second control code based on the deserialized second equalization signal.

    ELECTRONIC DEVICE AND OPERATING METHOD OF A DECODER

    公开(公告)号:US20230421671A1

    公开(公告)日:2023-12-28

    申请号:US18244107

    申请日:2023-09-08

    CPC classification number: H04L69/324 H04L47/43

    Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

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