公开(公告)号：US20170179146A1

公开(公告)日：2017-06-22

申请号：US15448697

申请日：2017-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINTAEK PARK ,  YOUNGWOO PARK ,  JAEDUK LEE

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11575

CPC classification number: H01L27/11573 ,  G11C5/02 ,  G11C5/025 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.