公开(公告)号：US20160047853A1

公开(公告)日：2016-02-18

申请号：US14673490

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： IN-WOOK OH ,  Chin Kim ,  Sunhom Steve Paak ,  Jae-Seok Yang

IPC: G01R31/26

CPC classification number: G01R31/2607 ,  G01R31/2601 ,  G01R31/31722 ,  G01R31/318511 ,  G01R31/31926

Abstract: A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.

Abstract translation: 测试系统包括行解码器，列解码器，行测试控制器和测试电路。 行解码器基于多个行输入信号来激活第一至第M行信号中的一个。 列解码器基于多个列输入信号来激活第一至第N列信号中的一个。 当行测试使能信号被激活时，行测试控制器首先输出第N列输出信号，这些信号被激活。 当行测试使能信号被去激活时，行测试控制器分别输出第一至第N列信号作为第一至第N列输出信号。 测试电路包括第一至第M行测试块，每个测试块包括第一至第N个测试单元。 当行测试使能信号被激活时，测试电路同时执行包括在行测试块中的第一至第N测试单元的短测试。

公开(公告)号：US10474783B2

公开(公告)日：2019-11-12

申请号：US15701971

申请日：2017-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth Rastogi ,  Subhash Kuchanuri ,  Chul-Hong Park ,  Jae-Seok Yang

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118

Abstract: A method of designing a layout of a semiconductor device includes designing layouts of cells, each layout including first conductive lines, the first conductive lines extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, disposing the layouts of the cells to be adjacent to each other in the first direction, such that the first conductive lines in adjacent layouts of the cells are connected to each other, and disposing insulation blocks at a boundary area between adjacent ones of the layouts of the cells or in areas of the layouts of the cells adjacent to the boundary area, such that the insulation blocks block connections between some of the first conductive lines.

公开(公告)号：US10177093B2

公开(公告)日：2019-01-08

申请号：US15497283

申请日：2017-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US09575112B2

公开(公告)日：2017-02-21

申请号：US14673490

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Wook Oh ,  Chin Kim ,  Sunhom Steve Paak ,  Jae-Seok Yang

IPC: G01R31/36 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/319

CPC classification number: G01R31/2607 ,  G01R31/2601 ,  G01R31/31722 ,  G01R31/318511 ,  G01R31/31926

Abstract: A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.

Abstract translation: 测试系统包括行解码器，列解码器，行测试控制器和测试电路。 行解码器基于多个行输入信号来激活第一至第M行信号中的一个。 列解码器基于多个列输入信号来激活第一至第N列信号中的一个。 当行测试使能信号被激活时，行测试控制器首先输出第N列输出信号，这些信号被激活。 当行测试使能信号被去激活时，行测试控制器分别输出第一至第N列信号作为第一至第N列输出信号。 测试电路包括第一至第M行测试块，每个测试块包括第一至第N个测试单元。 当行测试使能信号被激活时，测试电路同时执行包括在行测试块中的第一至第N测试单元的短测试。