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公开(公告)号:USD872116S1
公开(公告)日:2020-01-07
申请号:US29657869
申请日:2018-07-26
设计人: Daewon Kim , Jaewon Park , Hyunyeul Lee , Jiyoung Han , Hyungmin Kim
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12.
公开(公告)号:US20240249051A1
公开(公告)日:2024-07-25
申请号:US18449304
申请日:2023-08-14
发明人: Sungoh Ahn , Jaewon Park
IPC分类号: G06F30/327
CPC分类号: G06F30/327
摘要: Disclosed is a memory device, which includes a logic circuit that receives a first signal and a second signal from an external host, an output circuit that receives a first logic operation result or a second logic operation result from the logic circuit, a first logic gate that receives the first signal or the second signal and performs a third logic operation to output a third signal, a second logic gate that receives the first signal and the second signal and performs a fourth logic operation to output a fourth signal, and a multiplexer that receives the third signal and the fourth signal, receives the first logic operation result or the second logic operation result from the output circuit, and outputs one of the third signal and the fourth signal as a fifth signal in response to the first or second logic operation results.
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公开(公告)号:USD932506S1
公开(公告)日:2021-10-05
申请号:US29715356
申请日:2019-12-02
设计人: Daewon Kim , Jaewon Park , Hyunyeul Lee , Jiyoung Han , Hyungmin Kim
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公开(公告)号:USD851110S1
公开(公告)日:2019-06-11
申请号:US29615824
申请日:2017-08-31
设计人: Hyosang Bang , Sookkyung Lee , Ahrem Nam , Jaewon Park , Misook Yu , Junho Lee , Seungkyung Lim
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公开(公告)号:USD821435S1
公开(公告)日:2018-06-26
申请号:US29612136
申请日:2017-07-28
设计人: Daewon Kim , Hyun Yeul Lee , Insheik Martin Jung , Hyosang Bang , Youngseong Kim , Jaewon Park , Jiyoung Han
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