公开(公告)号：US11799010B2

公开(公告)日：2023-10-24

申请号：US17227456

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Jinwook Jung ,  Seunggeol Nam ,  Wontaek Seo ,  Insu Jeon

IPC: H01L29/45

CPC classification number: H01L29/45

Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

公开(公告)号：US11004949B2

公开(公告)日：2021-05-11

申请号：US16238706

申请日：2019-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Jinwook Jung ,  Seunggeol Nam ,  Wontaek Seo ,  Insu Jeon

IPC: H01L31/119 ,  H01L29/45

Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

公开(公告)号：US20200044041A1

公开(公告)日：2020-02-06

申请号：US16238706

申请日：2019-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Jinwook Jung ,  Seunggeol Nam ,  Wontaek Seo ,  Insu Jeon

IPC: H01L29/45

Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

公开(公告)号：US20190207593A1

公开(公告)日：2019-07-04

申请号：US16103233

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jae-Woo SEO ,  Youngsoo Shin ,  Jinwook Jung

IPC: H03K3/3562 ,  H03K3/037 ,  G01R31/3185 ,  H01L27/02 ,  G01R31/317

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.