公开(公告)号：US20230195636A1

公开(公告)日：2023-06-22

申请号：US18072929

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heonsoo LEE ,  Byungchul HONG ,  Junseok PARK ,  Jaehun CHUNG

IPC: G06F12/0862 ,  G06F12/06 ,  G06F12/02 ,  G06F9/38

CPC classification number: G06F12/0862 ,  G06F12/0646 ,  G06F12/0261 ,  G06F9/3816

Abstract: In some embodiments, a multi-port queueing cache includes a plurality of first ports, a plurality of second ports, a plurality of request handlers respectively coupled to the plurality of first ports, a cache storage unit coupled to the plurality of second ports, a reserve interface configured to exchange at least one address and at least one reserved cache line number, and a request interface configured to exchange the at least one reserved cache line number and at least one data. The reserve interface and the request interface are disposed between the plurality of request handlers and the cache storage unit. The cache storage unit includes a plurality of cache lines configured to store the plurality of data. The cache storage unit is configured to output a portion of the plurality of addresses, and receive a portion of the plurality of data corresponding to the portion of the plurality of addresses.

公开(公告)号：US20220188612A1

公开(公告)日：2022-06-16

申请号：US17496037

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junseok PARK ,  Suknam Kwon ,  Changsoo Park

IPC: G06N3/063

Abstract: A method of generating an output feature map based on an input feature map, the method including: generating an input feature map vector for a plurality of input feature map blocks when the number of channels of the input feature map is less than a certain number of reference channels; performing a convolution operation on the input feature map based on a target weight map and an additional weight map that has a weight identical to that of the target weight map, when the target weight map numbers less than a reference number; and generating an output feature map based on the performed convolution operation.

公开(公告)号：US20210174179A1

公开(公告)日：2021-06-10

申请号：US16989391

申请日：2020-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook SONG ,  Daekyeung KIM ,  Junseok PARK ,  Joonho SONG ,  Sehwan LEE ,  Junwoo JANG ,  Yunkyo CHO

IPC: G06N3/063 ,  G06F7/485

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.