公开(公告)号：US20250081459A1

公开(公告)日：2025-03-06

申请号：US18601009

申请日：2024-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUSEONG NOH ,  KWANG-SOO KIM ,  ILHO MYEONG

IPC: H10B43/27 ,  H01L21/28 ,  H01L23/528 ,  H01L25/065 ,  H01L29/51 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A three-dimensional semiconductor memory device may include a stack including gate electrodes and insulating layers, which are alternatingly stacked on a substrate, vertical channel structures penetrating the stack, and data storage patterns between the stack and the vertical channel structures. The data storage patterns may be spaced apart from each other in a direction perpendicular to a top surface of the substrate, and each of the data storage patterns may include a ferroelectric pattern, an anti-ferroelectric pattern, and a first insulating pattern.

公开(公告)号：US20250046757A1

公开(公告)日：2025-02-06

申请号：US18589650

申请日：2024-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  JAESIC LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H10B80/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a base die that includes first dummy pads on an edge at a top surface of the base die; a plurality of memory dies on the base die; a plurality of conductive posts spaced apart from the memory dies and on the edge of the base die; a mold layer that covers the base die, the memory dies, and the conductive posts; and a heat spreader that includes second dummy pads on an edge at a bottom surface of the heat spreader and third dummy pads on a central portion of the bottom surface of the heat spreader, wherein the heat spreader is disposed on the memory dies and the mold layer. The first dummy pads are correspondingly connected to the second dummy pads through the conductive posts and the second dummy pads are in contact with the conductive posts.

公开(公告)号：US20250015048A1

公开(公告)日：2025-01-09

申请号：US18405107

申请日：2024-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  SANG CHEON PARK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H10B80/00

Abstract: A semiconductor stack structure includes: a plurality of semiconductor dies vertically stacked on each other; and one or more dummy dies positioned between the plurality of semiconductor dies, wherein each of the one or more dummy dies includes: a dummy die base; a first interconnection structure positioned on a first side of the dummy die base and including a plurality of first bonding pads, wherein the first bonding pads are positioned at substantially regular intervals; and a second interconnection structure positioned on a second side of the dummy die base and including a plurality of second bonding pads, wherein the second bonding pads are positioned at substantially regular intervals.