公开(公告)号：US09436833B2

公开(公告)日：2016-09-06

申请号：US14499724

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Myung Na ,  Kee-Moon Chun

IPC: G06F21/72 ,  G06F21/60

CPC classification number: G06F21/60 ,  G06F21/71 ,  G06F21/84

Abstract: A security circuit may include a functional circuit including a test chain that connects flip-flops to verify hardware of the functional circuit, the functional circuit configured to generate an output signal by encrypting an input signal based on a control signal, a mode signal, and the chain; and/or a test controller configured to generate the input, control, and mode signals, and configured to generate an authentication result based on the output signal. A security circuit may include a first device including a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second and third signals and the chain; and/or a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal.

Abstract translation: 安全电路可以包括功能电路，其包括连接触发器以验证功能电路的硬件的测试链，所述功能电路经配置以通过基于控制信号，模式信号和模式信号加密输入信号来产生输出信号 连锁，链条; 和/或测试控制器，被配置为生成输入，控制和模式信号，并且被配置为基于输出信号生成认证结果。 安全电路可以包括在测试链中包括多个触发器的第一设备，第一设备被配置为接收第一，第二和第三信号，并且被配置为通过基于第二信号加密第一信号来生成第四信号 和第三信号和链; 和/或第二设备，被配置为生成所述第一，第二和第三信号，并且被配置为基于所述第四信号生成认证结果。

公开(公告)号：US09384855B2

公开(公告)日：2016-07-05

申请号：US14076300

申请日：2013-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Han Lee ,  Eun-Ji Kang ,  Jae-Sop Kong ,  Kee-Moon Chun

IPC: G06F1/00 ,  G11C29/02 ,  G11C11/56 ,  G06F3/00

CPC classification number: G11C29/023 ,  G11C11/5642

Abstract: Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

Abstract translation: 示例性实施例公开了包括特殊功能寄存器（SFR）的片上系统（SoC）及其操作方法。 SFR包括第一更新存储元件，第二更新存储元件，对应于第一更新存储元件的第一更新逻辑，以及对应于第二更新存储元件的第二更新逻辑，其中时钟被提供给第一更新存储器 响应于所述第一更新逻辑被启用，并且响应于所述第二更新逻辑被使能而将所述时钟提供给所述第二更新存储元件。