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    System-on-chip and method of operating the same
    1.
    发明授权
    System-on-chip and method of operating the same 有权
    系统级芯片及其操作方法

    公开(公告)号：US09519487B2

    公开(公告)日：2016-12-13

    申请号：US14161838

    申请日：2014-01-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Han Lee ,  Sung-Chul Yoon ,  Sung-Hoo Choi ,  Jae-Sop Kong ,  Kee-Moon Chun

    IPC: G06F9/38 ,  G06F15/78 ,  G06F9/30

    CPC classification number: G06F9/3877 ,  G06F15/7807

    Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

    Abstract translation: 片上系统（SoC）包括从属知识产权（IP）块，主IP块和更新控制单元。 从属IP块被配置为基于存储在第一存储单元中的第一控制信息对第一数据执行第一处理。 主IP块被配置为响应于接收到通过对第一数据执行第一处理获得的第一处理结果而对第二数据执行第二处理。 执行第二处理是基于存储在第二存储单元中的第二控制信息。 更新控制单元被配置为响应于执行第一处理而确定第一控制信息的更新时间或第二控制信息的更新时间，并执行第二处理。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160372593A1

    公开(公告)日：2016-12-22

    申请号：US15052177

    申请日：2016-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hyun YOO ,  Kwan-Young Kim ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Yong-Woo Jeon

    IPC: H01L29/78 ,  H01L21/324 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7816 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7851

    Abstract: A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.

    Abstract translation: 半导体器件包括：第一阱，其布置在衬底中并且包括第一导电类型的第一杂质;第二阱，设置在衬底中，包括不同于第一导电类型的第二导电类型的第二杂质，并且首先 第三部分和形成在第一阱和第二阱上的栅极结构，其中第二部分设置在第一部分和第三部分之间，第一部分和第三部分形成得比第二部分更深，并且浓度 第一部分和第三部分的第二杂质大于第二部分的第二杂质的浓度。

    Methods of forming semiconductor devices including an embedded stressor, and related apparatuses
    3.
    发明授权
    Methods of forming semiconductor devices including an embedded stressor, and related apparatuses 有权
    形成包括嵌入式应力源的半导体器件的方法及相关装置

    公开(公告)号：US09240460B2

    公开(公告)日：2016-01-19

    申请号：US14323007

    申请日：2014-07-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun-Suk Kim ,  Kee-Moon Chun

    IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32

    CPC classification number: H01L29/66545 ,  H01J37/32669 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7854

    Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming preliminary trenches adjacent opposing sides of an active region. The method includes forming etching selection regions in portions of the active region that are exposed after forming the preliminary trenches. The method includes forming trenches by removing the etching selection regions. Moreover, the method includes forming a stressor in the trenches. Related apparatuses are also provided.

    Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法包括在有源区的相对侧邻近地形成预备沟槽。 该方法包括在形成预备沟槽之后暴露的有源区的部分形成蚀刻选择区。 该方法包括通过去除蚀刻选择区域来形成沟槽。 此外，该方法包括在沟槽中形成应力源。 还提供了相关装置。

    METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING AN EMBEDDED STRESSOR, AND RELATED APPARATUSES
    7.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING AN EMBEDDED STRESSOR, AND RELATED APPARATUSES 有权
    形成嵌入式压力器的半导体器件的方法及相关装置

    公开(公告)号：US20150140757A1

    公开(公告)日：2015-05-21

    申请号：US14323007

    申请日：2014-07-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun-Suk Kim ,  Kee-Moon Chun

    IPC: H01L29/66 ,  H01L21/67

    CPC classification number: H01L29/66545 ,  H01J37/32669 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7854

    Abstract: Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming preliminary trenches adjacent opposing sides of an active region. The method includes forming etching selection regions in portions of the active region that are exposed after forming the preliminary trenches. The method includes forming trenches by removing the etching selection regions. Moreover, the method includes forming a stressor in the trenches. Related apparatuses are also provided.

    Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法包括在有源区的相对侧邻近地形成预备沟槽。 该方法包括在形成预备沟槽之后暴露的有源区的部分形成蚀刻选择区。 该方法包括通过去除蚀刻选择区域来形成沟槽。 此外，该方法包括在沟槽中形成应力源。 还提供了相关装置。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10056479B2

    公开(公告)日：2018-08-21

    申请号：US14993108

    申请日：2016-01-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Jong-Sung Jeon

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

    CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/165 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

    Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

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