公开(公告)号：US10541690B2

公开(公告)日：2020-01-21

申请号：US15443060

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangheon Lee ,  Jaehyun Kim ,  Kiyoung Choi ,  Soojung Ryu

IPC: H03L7/00 ,  H03L7/081 ,  H03L7/091 ,  G06F1/08 ,  G06F1/12

Abstract: In a method and device to align phases of a first clock signal and a second clock signal, include a phase detector, a delay generator, and a controller. The phase detector is configured to generate a preceding signal and a succeeding signal with respect to the first clock signal to detect a relationship between phases of the first clock signal and the second clock signal. The delay generator is configured to delay the first clock signal when the second clock signal falls behind the succeeding signal with respect to the first clock signal. The controller is configured to determine whether the phases of the first clock signal and the second clock signal are aligned with each other according to the relationship detected by the phase detector.

公开(公告)号：US10482033B2

公开(公告)日：2019-11-19

申请号：US15467104

申请日：2017-03-23

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Sangheon Lee ,  Dongwoo Lee ,  Kiyoung Choi ,  Soojung Ryu

IPC: G06F12/126 ,  G06F12/0895

Abstract: A memory controller includes a dirty group detector configured to, in response to receiving a request for writing data to a memory, modify addresses of a cache group related to a physical address of the memory, increase counters corresponding to the modified addresses of the cache group, and detect whether the cache group is in a dirty state based on the counters; and a dirty list manager configured to manage the cache group in the dirty state and a dirty list including dirty bits according to a result of the detecting; wherein the dirty bits indicate whether a cache set included in the cache group is in the dirty state.