公开(公告)号：US20210311104A1

公开(公告)日：2021-10-07

申请号：US17061380

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh ,  Minjae Lee ,  Unho Cha

IPC: G01R31/26 ,  H01L23/552 ,  H01L23/522 ,  H01L23/528 ,  H01L23/50

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop passing through the left-bottom corner region, a second conduction loop passing through the right-bottom corner region, a third conduction loop passing through the left-bottom corner region and the left-upper corner region, a fourth conduction loop passing through the right-bottom corner region and the right-upper corner region, and a shielding loop to shield electrical interference between the first through fourth conduction loops. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US12224759B2

公开(公告)日：2025-02-11

申请号：US17863167

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaerin Lee ,  Yang Azevedo Tavares ,  Minjae Lee ,  Kyeongkeun Kang

IPC: H03M1/10 ,  H03M1/06

Abstract: An apparatus and a method of correcting a mismatch of a time-interleaved analog-to-digital converter are provided. The apparatus may include: a time-interleaved analog-to-digital converter configured to receive a non-return-to-zero (NRZ) signal in a correction mode and generate a first output signal, and including a plurality of analog-to-digital converters; and a mismatch corrector configured to generate a second output signal by processing the first output signal of the time-interleaved analog-to-digital converter based on parameters, wherein the parameters may be generated based on the first output signal of the time-interleaved analog-to-digital converter in the correction mode, and a period of the NRZ signal may be different from a product of a sampling period of the time-interleaved analog-to-digital converter and a number of the plurality of analog-to-digital converters included in the time-interleaved analog-to-digital converter.

公开(公告)号：US11796587B2

公开(公告)日：2023-10-24

申请号：US17061380

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Roh ,  Minjae Lee ,  Unho Cha

IPC: G01R31/26 ,  H01L23/50 ,  H01L23/552 ,  H01L23/528 ,  H01L23/522

CPC classification number: G01R31/2607 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/552

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop passing through the left-bottom corner region, a second conduction loop passing through the right-bottom corner region, a third conduction loop passing through the left-bottom corner region and the left-upper corner region, a fourth conduction loop passing through the right-bottom corner region and the right-upper corner region, and a shielding loop to shield electrical interference between the first through fourth conduction loops. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.